检索结果-内蒙古大学图书馆

A new floorplanning method based on linear programming

WSEAS Transactions on Computers 2006年第11期5卷 2874-2879页

作者： Zhao, Changhong Chen, Jian Zhou, Xiaofang Jing, Ming'e Zhou, Dian ASIC and System State Key Lab. Fudan University Rd. Zhangheng No.825 Shanghai 201203 China

This paper analyses the floorplanning methods based on linear programming and presents a linear replacement of the non-linear objective function. It also presents the sub-section linearization method to replace the original nonlinear items in the constraint inequalities. Compared with former floorplanning methods based on linear programming, the solutions of the method in this paper always lie in the feasible region of the original floorplanning problem. Experimental results show that the method in this is competitive.

关键词： Linear programming

来源：评论

学校读者我要写书评

暂无评论

A 4.8-GHz Fully Integrated CMOS Integer-N PLL Frequency Synthesizer for WLAN

A 4.8-GHz Fully Integrated CMOS Integer-N PLL Frequency Synt...

引用

International Symposium on Communications and Information Technologies (ISCIT)

作者： Kangmin Hu Xiaofeng Yi Ye zhou Yumei Huang Zhiliang Hong State Key Lab of ASIC & System Fudan University Shanghai China Accel Semiconductor Shanghai China

In this paper, a 4.8 GHz fully integrated low power, low phase noise phase-locked loop (PLL) frequency synthesizer ready for WLAN application is presented. It is implemented in a 0.18 mum IP6M CMOS process. The chip consumes only 16 mA (including local buffers to the receiver and transmitter) from a 1.8 V supply and occupies an area of 1.85times1.1 mm 2 . From measurements, its in-band phase noise is -55.8 dBc/Hz and out-of-band phase noise is -119 dBc/Hz at 3 MHz offset. With the help of digital controlled capacitor array (DCCA) this frequency synthesizer can lock from 4.2 - 4.82 GHz

关键词： Phase locked loops Frequency synthesizers Wireless LAN Phase noise CMOS process Transmitters Noise measurement Phase measurement Semiconductor device measurement Digital control

来源：评论

学校读者我要写书评

暂无评论

Application of wavelets in circuit modeling and simulation

Application of wavelets in circuit modeling and simulation

引用

Progress in Electromagnetics Research Symposium 2006, PIERS 2006 Tokyo

作者： Zeng, Xuan Yang, Fan Zhou, Dian Cai, Wei ASIC and System State Key Lab. Microelectronics Dept. Fudan University China E. E. Dept. University of Texas Dallas United States Math. Dept. University of North Carolina Charlotte United States

ISBN: (纸本)9781629939513

As SOC chips develop to higher and higher frequency, the singularity problem in high speed circuits has remarkably challenged the accuracy and computation time of the state-of-the-art circuit simulators. Taking advantage of the local support and multi-resolution properties of wavelets, the singularity problem in high speed circuits can be efficiently handled by wavelet collocation method with adaptive scheme. The last decade has seen the development of wavelet theory for solving ODE/PDE and its applications in simulation of high speed and large scale linear and nonlinear circuits. This survey will review a series of wavelet theories and fast computation techniques in the transient, steady state and noise analysis of nonlinear circuits, and model order reduction and fast simulation of linear interconnect circuits, as well as analog behavioral modeling. Compared with the traditional approaches using global support functions, the wavelet methods can significantly improve the simulation speed and accuracy, and consequently establish a new direction for high speed circuit simulation.

关键词： Circuit simulation

来源：评论

学校读者我要写书评

暂无评论

Exact minimization of large fixed polarity dual form of reed-muller functions

Exact minimization of large fixed polarity dual form of reed...

引用

ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Yang, M. Xu, H. Wang, L. Tong, J.R. Almaini, A.E.A. State Key Lab of ASIC and System Microelectronics Dept. Fudan University Shanghai 201203 China Tianjin Vocational College of Mechanics and Electricity Tianjin China School of Engineering Napier University Edinburgh EH10 5DT United Kingdom

ISBN: (纸本)1424401615

Dual Form of Reed-Muller (DFRM) expansions are implemented in OR/XNOR logic, which are based on the features of coincidence operation and known as fixed polarity Canonical OR-Coincidence (COC) expansions. An efficient minimization method is proposed to find the best polarity COC expansion for large functions. The method derives one expansion from another adjacent polarity expansion using gray code, resulting in small space complexity O(M) and time complexity O(2nMlogM) (n and M are the number of input variables and the number of on-set COC maxterms). Hence, it makes minimization for large functions practical. ©2006 IEEE.

关键词： Logic circuits

来源：评论

学校读者我要写书评

暂无评论

Heel Crack and Lead-Free Soldering Issues Affecting Power Electronics Packages

Heel Crack and Lead-Free Soldering Issues Affecting Power El...

引用

IEEE Region 10 International Conference TENCON

作者： Lunwen He Shaohui Pan Lk Wang David Wei Zhang Agency for Science Technology and Research (ASTAR) Shanghai China ASIC & System State Key Lab of Fudan University Shanghai China

Heel crack is one of the most complicated reliability problems of wire bonding in the power electronic package. In this work, we investigate the effects of solder IR reflow to the heel crack both in experimental and FEA simulation study for the 2-5 mil (diameter) aluminum wire. The results show that the plastic strain at the heel region induced by the wire bonding process, influence of molding process and the coefficient of thermal expansion (CTE) mismatches between different components in package are the main causes of heel crack happened in IR reflow. With respect to the trend of lead free, the simulation is also processed under the three temperature hierarchies with different peak reflow temperature (220 D, 240 D, 260 D) and wetting time. From von mises stress and related plastic strain distributions, it can been seen that, during the reflow, the heel region of the wire is endured larger stress and plastic strain than other areas, and with the peak reflow temperature and wetting time increasing, the plastic strain also increases about 20%, which is very critical for material fatigue

关键词： Environmentally friendly manufacturing techniques Lead Soldering Power electronics Electronics packaging Wire Plastics Capacitive sensors Temperature Stress

来源：评论

学校读者我要写书评

暂无评论

Characteristics of Si-Sb-Te films for phase change memory

Characteristics of Si-Sb-Te films for phase change memory

引用

2006 MRS Spring Meeting

作者： Jie, Feng Yin, Zhang Baowei, Qiao Yanfei, Cai Yinyin, Lin Tingao, Tang Bingchu, Cai Bomy, Chen Key Lab. for Thin Film and Microfabrication Shanghai Jiao Tong University Ministry of Education 1954 Huasan Road Shanghai 200030 China State Key Laboratory of ASIC System Fudan University Shanghai 200433 China Silicon Storage Technology Inc. 1171 Sonora Court Sunnyvale CA 94086

The novel phase change materials Si-Sb-Te films were prepared. The crystallization temperature of films increases with the increasing of Si concentration. Phase separation was observed in the Si-Sb-Te films, the dominant phase is Sb2Te3. The melting temperature of Si-Sb-Te decreased to ∼550°C lower than 640°C of Ge2Sb 2Te5. The decrease of film thickness of Si-Sb-Te films is less than 2% after annealing at 400°C, which is less than ∼7% of the film thickness change of Ge2Sb2Te5 film. The crystalline resistivity of Si-Sb-Te films increased and the ratio of amorphous/crystalline resistivity of Si-Sb-Te films increased also comparing with Ge2Sb2Te5 film, which is benefit to reduce the writing current and keep higher on/off ratio of phase change memory. Reversible switching was performed in the devices with Si-Sb-Te films. The device with Si14.3Sb28.6Te57.2 film can be programmed with a 100 ns SET pulse and a 20 ns RESET pulse. The Reset current is only 1.37mA for a 10μm-sized device. © 2006 Materials Research Society.

关键词： Thin films

来源：评论

学校读者我要写书评

暂无评论

Exact Minimization of Large Fixed Polarity Dual Form of Reed-Muller Functions

Exact Minimization of Large Fixed Polarity Dual Form of Reed...

引用

2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： M.Yang H.Xu L.Wang J.R.Tong A.E.A.Almaini State Key Lab of ASIC ＆ System Microelectronics Dept.Fudan University Tianjin Vocational College of Mechanics and Electricity School of Engineering Napier University

ISBN: (纸本)1424401607

Dual Form of Reed-Muller（DFRM） expansions are implemented in OR/XNOR logic,which are based on the features of coincidence operation and known as fixed polarity Canonical OR-Coincidence（COC） expansions. An efficient minimization method is proposed to find the best polarity COC expansion for large *** method derives one expansion from another adjacent polarity expansion using gray code,resulting in small space complexity O（M） and time complexity O（2~nM/ogM）(n and M are the number of input variables and the number of on-set COC maxterms).Hence,it makes minimization for large functions practical.

关键词： Logic Synthesis Optimization Dual Form of Reed-Muller EDA

来源：评论

学校读者我要写书评

暂无评论

Some solutions for writing current reduction and high density application of phase change memory

Some solutions for writing current reduction and high densit...

引用

ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Lin, Yinyin Feng, Jie Cai, Yaifei Lv, Hangbing Liao, Feifei Liu, Xin Tang, Tingao Qiao, Baowei Lai, Yunfeng Zhang, Yi Cai, Bingchu Chen, Bomy Department of Microelectronics ASIC and System State Key Lab. Fudan University Shanghai 200433 China Research Institute of Micro/Nanometer Technology Shanghai Jiao Tong University Shanghai 200030 China Silicon Storage Technology Inc. 1171 Sonora Court Sunnyvale CA 94086 United States

High writing current is the bottle-neck of PCM application and efforts focus on merely materials doping to improve crystal resistivity, novel structure to decrease active area etc. Here some solutions of our group are... 详细信息

ISBN: (纸本)1424401615

关键词： Phase change memory

来源：评论

学校读者我要写书评

暂无评论

Electrical properties of metamorphic in0.52Al 0.48As/In0.65Ga0.35As HEMT's on GaAs substrate

Electrical properties of metamorphic in0.52Al 0.48As/In0.65G...

引用

ICSICT-2006: 2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Qiu, Z.J. Liu, R. Zhang, S.L. Gui, Y.S. Cui, L.J. Zeng, Y.P. Chu, J.H. School of Microelectronics Fudan University Shanghai 200433 China State Key Lab. of ASIC System and Micro/Nanoelectronics Science and Technology Innovation Platform Fudan University Shanghai 200433 China National Laboratory for Infrared Physics Shanghai Institute of Technical Physics Chinese Academy of Sciences Shanghai 200083 China Institute of Semiconductors Chinese Academy of Sciences Beijing 10008 China

ISBN: (纸本)1424401615

Variable magnetic field Hall measurements were performed to investigate the electrical properties in In0.52Al0.48As/In 0.65Ga0.35As metamorphic high electron mobility transistors (MMHEMT's) on GaAs substrate at the temperature range from 4 to 100 K. The Shubnikov-de Hass (SdH) measurement shows the two-dimensional electronic behavior and two-subband electron occupation in MMHEMT's. The electron densities and mobilities of the two subbands are obtained by fast Fourier transform analysis. Both the SdH oscillations and conventional Hall analysis are in good agreement in the determination of total electron density, which is about 2.1×1012 cm-2 due to incomplete transfer of the electrons. The temperature dependence of the electron mobility indicates that at low temperature alloy scattering dominates, whereas at high temperature, the mobility is mainly limited by optical phonon scattering. © 2006 IEEE.

关键词： High electron mobility transistors

来源：评论

学校读者我要写书评

暂无评论

FPGA PLACEMENT OPTIMIZATION BY TWO-STEP UNIFIED GENETIC ALGORITHM AND SIMULATED ANNEALING ALGORITHM

引用

Journal of Electronics(China) 2006年第4期23卷 632-636页

作者： Yang Meng A.E.A. Almaini Wang Pengjun School of Engineering Napier University 10 Colinton Road.Edinburgh EH10 5DT UK State Key Lab of ASIC ＆ System Microelectronics Dept Fudan University Shanghai 201203 China Institute of Circuits and Systems Ningbo University Ningbo 315211. China

Genetic Algorithm (GA) is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it avoids converging to the local optimum. However, it takes too much CPU time in the late process of GA. On the other hand, in the late process Simulated Annealing (SA) converges faster than GA but it is easily trapped to local optimum. In this letter, a useful method that unifies GA and SA is introduced, which utilizes the advantage of the global search ability of GA and fast convergence of SA. The experimental results show that the proposed algorithm outperforms GA in terms of CPU time without degradation of performance. It also achieves highly comparable placement cost compared to the state-of-the-art results obtained by Versatile Place and Route (VPR) Tool.

关键词： Genetic Algorithm （GA） Simulated Annealing （SA） Placement FPGA EDA

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：