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Asia and South Pacific Design Automation Conference

作者： Xingyu Tong Zhijie Cai Peng Zou Min Wei Yuan Wen Zhifeng Lin Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China Zhangjiang Fudan International Innovation Center Fudan University Shanghai China

The expansion of the IC dimension is ushering in a more-than-Moore era, necessitating corresponding EDA tools. Existing TSV-based 3D placers focus on minimizing cuts, while burgeoning F2F-bonded ICs features dense interconnection between two planar die. Towards this novel structure, we proposed an integrated adaptation methodology upon mature one-die-based placement strategies. First, we instructively utilized a one-die placer to provide a statistical looking-ahead net diagnosis. The netlist henceforth shall be coarsened topologically and geometrically with a multi-level framework. Level by level, the partition will be refined according to a multi-objective gain formulation, including cut expectation, heterogeneous row height, and balanced cell distribution. Given the partition, we synchronized the behavior of analytical planar placers by balancing the density and wirelength objective function among asymmetric layers. Finally, the result will be further improved by heuristic bonding terminals’ detail placement and a post-place partition adjustment. Compared to the top three winners of the 2022 CAD Contest at ICCAD, experiment results show that our fine-grained fusion upon partitioning and placement gets the best normalized average wirelength with a fairly reasonable runtime under all 3D architectural constraints.

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Subgraph Matching with Diversity Handling and Its Applications to PCB Placement

Subgraph Matching with Diversity Handling and Its Applicatio...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Chuandong Chen Haiming Lin Miaodi Su Huan He Jianli Chen Ziran Zhu College of Physics and Information Engineering Fuzhou University Fuzhou China Fujian Science & Technology Innovation Laboratory for Optoelectronic Information of China Fuzhou China Hangzhou Huawei Enterprises Telecommunication Technologies Co. Ltd Hangzhou China State Key Lab of ASIC & System Fudan University Shanghai China National ASIC System Engineering Center Southeast University Nanjing China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

Printed circuit board (PCB) placement is a critical stage in industrial chip design, which still heavily relies on manual methods, leading to substantial design time consumption. Given the frequent occurrence of similar or identical modules in different PCB designs, the reuse of placements emerges as a promising avenue to enhance the efficiency of PCB placement. In this paper, we propose a sub graph matching based reference placement algorithm to achieve PCB placement reuse, thereby improving placement efficiency. We first take the netlist of the already placed and unplaced circuits as input and abstract them into graphs. Then, we construct and filter candidate spaces based on the characteristics of components and nets. In the process of filtering candidate spaces, we adopt diversity handling that includes cut edges and block nodes to ensure the proposed algorithm can handle inexact matching. Finally, we introduce virtual nodes to construct a matching tree using a combination of depth-first search (DFS) and breadth-first search (BFS), and then perform hierarchical matching based on this matching tree to complete the sub graph matching and obtain the placement results. Experimental results show that in large-scale PCB cases, our algorithm runs much faster than the state-of-the-art works. Particularly, the matching rate of our algorithm is almost 100% for the tested cases.

关键词： Matched filters Design automation Filtering Printed circuits Diversity reception DH-HEMTs Manuals

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Mining Lithography Hotspots from Massive SEM Images Using Machine Learning Model

Mining Lithography Hotspots from Massive SEM Images Using Ma...

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2021 China Semiconductor Technology International Conference, CSTIC 2021

作者： Zhou, Tao Xu, Bowen Li, Chen Diao, Xuling Yan, Yan Chen, Shoumian Zhao, Yuhan Zhou, Kan Zhou, Wenzhan Zeng, Xuan Shi, Xuelong Shanghai Integrated Circuits Rd Center Co. Ltd. Shanghai China State Key Lab of Asic System School of Microelectronics Fudan University Shanghai China

ISBN: (纸本)9781665449458

An effect method based on machine learning is developed for hotspots mining in lithography. A series of models are trained independently and combined to achieve high accuracy. Innovatively, contour information is firstly adopted to assist the hotspot detection, which eases the very challenging task of detection for topology aberration caused by complicated process effects. More importantly, the proposed method based on new methodology provides high efficiency which is competent for high volume manufacturing. © 2021 IEEE.

关键词： Machine learning

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High responsivity and flexible deep-UV phototransistor based on Ta-doped β-Ga_(2)O_(3)

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npj Flexible Electronics 2022年第1期6卷 457-465页

作者： Xiao-Xi Li Guang Zeng Yu-Chun Li Hao Zhang Zhi-Gang Ji Ying-Guo Yang Man Luo Wei-Da Hu David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan University200433 ShanghaiChina National Key Laboratory of Science and Technology on Micro/Nano Fabrication Shanghai Jiao Tong University200240 ShanghaiChina Shanghai Synchrotron Radiation Facility(SSRF) Zhangjiang LabShanghai Advanced Research Institute&Shanghai Institute of Applied PhysicsChinese Academy of Sciences201204 ShanghaiChina State Key Laboratory of Infrared Physics Shanghai Institute of Technical PhysicsChinese Academy of Sciences200083 ShanghaiChina

Deep-ultraviolet(DUV)phototransistors have shown great potential applications in UV imaging,artificial intelligence,and wearable *** a large number of wide bandgap semiconductors,the quasi-two-dimensionalβ-Ga_(2)O_(3) is considered as an ideal candidate for DUV photodetector ***,we report a high responsivity(R)and fully flexible Ta-dopedβ-Ga_(2)O_(3) DUV phototransistor which exhibits outstanding optoelectrical properties with a high R of 1.32×10^(6) A/W,a large detectivity of 5.68×10^(14) Jones,a great photo-to-dark current ratio of 1.10×10^(10)%,a high external quantum efficiency of 6.60×10^(8)%,and an ultra-fast response time of~3.50 ***,the flexible Ta-dopedβ-Ga_(2)O_(3) device also displays high reliability and mechanical flexibility that can sustain well after over 1×10^(4) bending ***,high-contrast imaging of UV light was obtained on the flexible DUV detector arrays,which can be efficiently trained and recognized by an artificial neural *** findings offer a perspective to develop wearable optoelectronics and UV imaging based on high-performance flexibleβ-Ga_(2)O_(3) DUV phototransistors,providing an inspiration for the future work in artificial intelligence and bionic robot fields.

关键词： transistor responsivity artificial

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Subgraph matching-based reference placement for printed circuit board designs

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The Journal of Supercomputing 2024年第16期80卷 24324-24357页

作者： Zhu, Ziran Li, Yilin Su, Miaodi Zhang, Shu Su, Haiyuan Xiao, Yifeng He, Huan Chen, Jianli Chang, Yao-Wen National ASIC System Engineering Center Southeast University Nanjing China College of Mathematics and Computer Science Fuzhou University Fuzhou China Department of Electrical Engineering University of Southern California Los Angeles USA Hangzhou Huawei Enterprises Telecommunication Technologies Co. Ltd Hangzhou China State Key Lab of ASIC and System Fudan University Shanghai China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Taiwan University Taipei Taiwan

Reference placement is promising to handle the increasing complexity in printed circuit board (PCB) designs, which aims to find the isomorphism of the placed template in component combination to reuse the placement. In this paper, we convert the netlist information into a graph and then model the reference placement as a subgraph matching problem. Since the state-of-the-art subgraph matching methods usually recursively search the solutions and suffer from high time and memory consumption in large-scale designs, we develop a novel subgraph matching algorithm D2BS with diversity tolerance and improved backtracking to guarantee matching quality and efficiency. The D2BS algorithm is founded on a data structure called the candidate space (CS) structure. We build and filter the candidate set for each query node according to our designed features to construct the CS structure. During the CS optimization process, a graph diversity tolerance strategy is adopted to achieve efficient inexact matching. Then, hierarchical matching is developed to search the template embeddings in the CS structure guided by branch backtracking and matched-node snatching strategies. Based on the industrial PCB designs, experimental results show that D2BS outperforms the state-of-the-art subgraph matching method in matching accuracy and running time.

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TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference

TCP-Net: Minimizing Operation Counts of Binarized Neural Net...

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IEEE International Symposium on Circuits and systems

作者： Qingliang Liu Jiabao Gao Jinmei Lai State Key Lab of ASIC and System Fudan University Shanghai China

Binarized neural network (BNN) dataflow inference accelerators have emerged as a promising solution to be applied in cost- and power-restricted domains, such as IoT and smart edge-devices. However, there still exists abundant redundancies in BNN inference, which severely limit the performances of these accelerators. To alleviate the performance degradation, we propose TCP-Net, an efficient architecture to minimize the number of operations in BNN inference while maintaining the original accuracy. Inspired by the observation that the processes of obtaining the outputs of multiple related kernels in BNNs contain significant repeated calculations, we first build a formula to bridge these outputs by utilizing the kernel inclusion similarity and eliminate the unnecessary operations. Through the recursive algorithm, we further convert each original XNOR-popcount convolution into threshold-comparable-popcount (TCP) operations, which can be implemented to directly achieve the final output without any extra steps. Furthermore, we reduce the remaining TCP operation counts by exploiting tile-based pruning strategy. Compared to the prior state-of-the-art designs, TCP-Net saves 79.11 percent of the operations without any accuracy loss, bringing 6.0× inference-speedup and 12.4× energy-efficiency improvement.

关键词： Convolution Redundancy Neural networks Computer architecture Energy efficiency Kernel Smart devices

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The Power of Graph Signal Processing for Chip Placement Acceleration

arXiv

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arXiv 2025年

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. Copyright © 2025, The Authors. All rights reserved.

关键词： Nonlinear programming

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A survey of FPGA design for AI era

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Journal of Semiconductors 2020年第2期41卷 14-19页

作者： Zhengjie Li Yufan Zhang Jian Wang Jinmei Lai State Key Lab of ASIC and System School of Microelectronics Fudan University

FPGA is an appealing platform to accelerate *** survey a range of FPGA chip designs for *** DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit *** other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of *** ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC *** other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of *** memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/*** designs are new architecture and specialized AI *** ACAP in 7 nm is the first industry adaptive compute acceleration *** AI engine can provide up to 8X silicon compute *** AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.

关键词： FPGA DNN Low-precision DSP CLB ALM

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Biofunctionalization-Optimized Mos2-Based Fet Biosensors for the Detection of Tau Protein

SSRN

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SSRN 2024年

作者： Wen, Xiaohong Zhao, Xuefeng Shan, Xinzhi Lu, Hongliang Gao, Xiumin Zhuang, Songlin Engineering Research Center of Optical Instrument and System Ministry of Education Shanghai Key Lab of Modern Optical System School of Optical-Electrical and Computer Engineering University of Shanghai for Science and Technology 516 Jungong Road Shanghai200093 China State Key Laboratory of High-Performance Ceramics and Superfine Microstructure Shanghai Institute of Ceramics Chinese Academy of Sciences Shanghai200050 China State Key Laboratory of ASIC System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Fudan University Shanghai200433 China

Field effect transistor (FET)-based biosensors can accurately quantify changes in weak signals and show excellent performance advantages in the detection of trace biological disease markers. Biological functionalization (biofunctionalization) is an important factor in the fabrication of FET-based biosensors, which directly affects the performance of the biosensor. However, little attention from researchers has been paid to biofunctionalization, which results in uneven performance of biosensors. Herein, MoS2-based FET biosensors are designed and fabricated using four different biofunctionalization methods. The most suitable biofunctionalization method is obtained by comparing the sensing performances of different functionalized MoS2-based FET biosensors. Moreover, the working mechanism of the optimized biofunctionalization method is explored. Besides, the biofunctionalization-optimized MoS2-based FET biosensor exhibits excellent sensing performance, achieving sensitive detection of Tau protein in the concentration range of 10-2~103 pg/mL. This study provides a universal and effective strategy for the biofunctionalization optimization of two-dimensional materials-based FET biosensors. © 2024, The Authors. All rights reserved.

关键词： Molybdenum compounds

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Biofunctionalization-Optimized MoS2-Based Fet Biosensors for the Detection of Tau Protein

SSRN

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SSRN 2024年

Field effect transistor (FET)-based biosensors can accurately quantify changes in weak signals and show excellent performance advantages in the detection of trace biological disease markers. Biological functionalization (biofunctionalization) is an important factor in the fabrication of FET-based biosensors, which directly affects the performance of the biosensor. However, little attention from researchers has been paid to biofunctionalization, which results in uneven performance of biosensors. Herein, MoS2-based FET biosensors are designed and fabricated using four different biofunctionalization methods. The most suitable biofunctionalization method is obtained by comparing the sensing performances of different functionalized MoS2based FET biosensors. Moreover, the working mechanism of the optimized biofunctionalization method is explored. Besides, the biofunctionalization-optimized MoS2-based FET biosensor exhibits excellent sensing performance, achieving sensitive detection of Tau protein in the concentration range of 10-2~103 pg/mL. This study provides a universal and effective strategy for the biofunctionalization optimization of two-dimensional materials-based FET biosensors. © 2024, The Authors. All rights reserved.

关键词： Molybdenum compounds

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