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Learning Sparse Patterns in Deep Neural Networks

Learning Sparse Patterns in Deep Neural Networks

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International Conference on asic

作者： Weijing Wen Fan Yang Yangfeng Su Dian Zhou Xuan Zeng State Key Lab of ASIC & System Fudan University Shanghai China Fudan University Shanghai China

Acceleration in deeper neural networks is hindered by high demand for computation and memory storage in resource constrained devices. In this paper, we propose a novel regularization method to learn hardware-friendly sparse structures for deep convolutional neural networks. A limited number of fixed sparse patterns are learned through the regularization and the filters are represented by these fixed sparse patterns. Our regularization method can produce compact models with higher degree of sparsity than the state-of-the-art structured sparsity learning method. The limited number of fixed sparse patterns also facilitate the hardware implementation. Our experiments on several deep neural networks with image classification tasks show that our proposed approach can achieve remarkably higher degree of sparsity with acceptable loss of accuracy.

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Anti-lotus leaf effect: smearing millions of picoliter droplets on bio-inspired artificial lotus leaf

Anti-lotus leaf effect: smearing millions of picoliter dropl...

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IEEE Conference on Nanotechnology

作者： Lin Du Yongheng Wei Antoine Riaud Jia Zhou ASIC and System State Key Lab School of Microelectronics Fudan University China State Key Laboratory of Genetic Engineering Fudan University China

Compartmentalization of aqueous samples into micro-droplets enables to study single cells or detect single molecules by performing large number of independent experiments. However, as the droplet size becomes smaller, the surface energy becomes larger so that micro-channels or surface treatments are required to break droplets below the picoliter range, resulting in an increased experimental or chemical complexity. Herein, we study the spontaneous liquid film breakup observed after smearing a mother droplet on the surface of lotus leave reversal. As the film breaks and recedes, it is mechanically trapped in single wells formed by the natural bulges on the leaf and forms picoliter droplets, which we called anti-lotus effect droplet. The bio-inspired effect has the advantage of resisting capillary forces and releasing surface tension in the three-phase interface. Using soft-lithography and spin-coating, we obtain the bio-mimetic wells array with the corrugated surface analogous with the lotus leave, which enables a deeper liquid penetration during the smearing step that results in a more efficient filling of the wells. In the present experiments, we have obtained a regular array of 2 pL droplets with a density of 62,500 droplets/cm 2 , which equivalents to 5.4 million droplets on the surface a 96 well plate. This bio-inspired method of forming droplet will be a convenient way to operate with no chemical treatment and seal. It undoubtedly decreases the complexity of chip manufacturing and potential interference by chemical treatments. We believe that such a method contributes to the development of the efficient micro-droplet generator with a pure physical interface and thus is applicable to biological and medical analysis.

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MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency

MajorityNets: BNNs Utilising Approximate Popcount for Improv...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Seyedramin Rasoulinezhad Sean Fox Hao Zhou Lingli Wang David Boland Philip H.W. Leong School of Electrical and Information Engineering The University of Sydney Australia State Key Lab of ASIC and System Fudan University Shanghai China

Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. With BNNs, multiply-accumulate (MAC) operations can be simplified to XnorPopcount operations, leading to massive reductions in both memory and computation resources. Furthermore, multiple efficient implementations of BNNs have been reported on field-programmable gate array (FPGA) implementations. This paper proposes a smaller, faster, more energy-efficient approximate replacement for the XnorPopcount operation, called XNorMaj, inspired by state-of-the-art FPGA look-up table schemes which benefit FPGA implementations. We show that XNorMaj is up to 2x more resource-efficient than the XnorPopcount operation. While the XNorMaj operation has a minor detrimental impact on accuracy, the resource savings enable us to use larger networks to recover the loss.

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PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks

PIR-DSP: An FPGA DSP Block Architecture for Multi-precision ...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： SeyedRamin Rasoulinezhad Hao Zhou Lingli Wang Philip H.W. Leong School of Electrical and Information Engineering The University of Sydney Australia State Key Lab of ASIC and System Fudan University Shanghai China

Quantisation is a key optimisation strategy to improve the performance of floating-point deep neural network (DNN) accelerators. Digital signal processing (DSP) blocks on field-programmable gate arrays are not efficiently utilised when the accelerator precision is much lower than the DSP precision. Through three modifications to Xilinx DSP48E2 DSP blocks, we address this issue for important computations in embedded DNN accelerators, namely the standard, depth-wise, and pointwise convolutional layers. First, we propose a flexible precision, run-time decomposable multiplier architecture for CNN implementations. Second, we propose a significant upgrade to DSPDSP interconnect, providing a semi-2D low precision chaining capability which supports our low-precision multiplier. Finally, we improve data reuse via a register file which can also be configured as FIFO. Compared with the 27 × 18-bit mode in the Xilinx DSP48E2, our Precision, Interconnect, and Reuseoptimised DSP (PIR-DSP) offers a 6× improvement in multiplyaccumulate operations per DSP in the 9 × 9-bit case, 12× for 4 × 4 bits, and 24× for 2 × 2 bits. We estimate that PIR-DSP decreases the run time energy to 31/19/13% of the original value in a 9/4/2-bit MobileNet-v2 DNN implementation.

关键词： Computer architecture Field programmable gate arrays Standards Convolution Integrated circuit interconnections Digital signal processing Neural networks

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Unijunction Transistor on Silicon-On-Insulator Substrate

Unijunction Transistor on Silicon-On-Insulator Substrate

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International Conference on Solid-state and Integrated Circuit Technology

作者： YX. Chen J. Liu K. Xiao A. Zaslavsky S. Cristoloveanu FY. Liu B. Li J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Brown University Providence RI USA IMEP-LAHC INP-Grenoble/Minatec CS 50257 Grenoble France Institute of Microelectronics Chinese Academy of Sciences Beijing China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

A unijunction transistor based on fully-depleted silicon-on-insulator substrate is proposed. The device structure is similar to a junction field effect transistor. By conducting the TCAD simulation, we observe sharp switching and large hysteresis in emitter current-emitter voltage curves with the turn-on voltage linearly controlled by the second base voltage. The operation of the device is mainly determined by the emitter-channel PN junction, which is induced by the backgate voltage. The impact of the backgate voltage on the electrical characteristics is analyzed by changes in the channel potential.

关键词： Substrates Silicon Junctions Hysteresis Electric potential Switches Voltage control

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A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Vertical RRAM and 0.014% Bit Error Rate Using In-Cell Stabilization Scheme for IoT Security Applications

A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Ve...

引用

International Electron Devices Meeting (IEDM)

作者： Jianguo Yang Dengyun Lei Deyang Chen Jing Li Haijun Jiang Qingting Ding Qing Luo Xiaoyong Xue Hangbing Lv Xiaoyang Zeng Ming Liu Zhejiang Lab Hangzhou China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China The No.5 Electronics Research Institute of the Ministry of Industry and Information Technology Guangzhou China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9781728188881

ISBN: (纸本)9781728188898

In this work, we propose and demonstrate a multi-layer 3-dimensional (3D) vertical RRAM (VRRAM) PUF with in-cell stabilization scheme to improve both cost efficiency and reliability. An 8-layer VRRAM array was manufactured with excellent uniformity and good endurance of >10 7 . Apart from the variation in RRAM resistance, enhanced randomness is obtained thanks to the parasitic IR drop and abundant sneak current paths in 3D VRRAM. To deal with the common issue of unstable bits in PUF output, in-cell stabilization is proposed by first employing asymmetric biasing to detect the unstable bits and then exploiting reprogramming to expand the deviation to stabilize the output. The bit error rate is reduced by >7X (68X) for 3(5) times reprogramming. The proposed PUF features excellent resistance against machine learning attack and passes both National Institute of Standards and Technology (NIST) 800-22 and NIST 800-90B test suites.

关键词： Training Temperature measurement Three-dimensional displays NIST Tin Reliability Testing

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Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method

Efficient Yield Analysis for SRAM and Analog Circuits using ...

引用

IEEE International Conference on Computer-Aided Design

作者： Xiao Shi Hao Yan Jiajia Zhang Qiancun Huang Longxing Shi Lei He State Key Lab of ASIC & System Fudan University China Southeast University China University of California Los Angeles CA USA

Performance failure has become the major threat to the robustness and reliability of various memory and analog circuits. It is challenging to accurately estimate the extremely small failure probability when failed samples are distributed in multiple disjoint failure regions. In this paper, we develop a novel meta-model based importance sampling (MIS) method. MIS utilizes Gaussian Process meta-model to construct quasi-optimal importance sampling distribution, and performs Markov Chain Monte Carlo (MCMC) simulation to generate new samples from the proposed distribution. By updating our global Importance Sampling estimator in an iterated framework, MIS leads to better efficiency and higher accuracy. For SRAM bit cell with single failure region, MIS uses 4-6X fewer samples and reaches better accuracy when compared to several recent methods. For a two-stage amplifier circuit with multiple failure schemes, MIS is 213X faster than MC without compromising accuracy, while other methods fail to cover all failure regions in our experiment.

关键词： Monte Carlo methods Design automation Random access memory Gaussian processes Analog circuits Markov processes Robustness

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An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *

An Efficient EPIST Algorithm for Global Placement with Non-I...

引用

Design Automation Conference

作者： Jianli Chen Zhipeng Huang Ye Huang Wenxing Zhu Jun Yu Yao-Wen Chang State Key Lab of ASIC & System Fudan University China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

With the increasing design requirements of modern circuits, a standard-cell library often contains cells of different row heights to address various trade-offs among performance, power, and area. However, maintaining all standard cells with integer multiples of a single-row height could cause some area overheads and increase power consumption. In this paper, we present an analytical placer to directly consider a circuit design with non-integer multiple-height standard cells and additional layout constraints. The region of different cell heights is adaptively generated by the global placement result. In particular, an exact penalty iterative shrinkage and thresholding (EPIST) algorithm is employed to efficiently optimize the global placement problem. The convergence of the algorithm is proved, and the acceleration strategy is proposed to improve the performance of our algorithm. Compared with the state-of-the-art works, experimental results based on the 2017 CAD Contest at ICCAD benchmarks show that our algorithm achieves the best wirelength and area for every benchmark. In particular, our proposed EPIST algorithm provides a new direction for effectively solving large-scale nonlinear optimization problems with non-smooth terms, which are often seen in real-world applications.

关键词： Standards Optimization Clustering algorithms Libraries Circuit synthesis Benchmark testing Iterative algorithms

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A review on Z2-FET and PISD based on Silicon-on-insulator substrate

A review on Z2-FET and PISD based on Silicon-on-insulator su...

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IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

作者： K. Xiao J. Liu JN. Deng X. Gong I J. Wan School of information science and technology State key lab of ASIC and System Fudan University China National University of Singapore (NUS) Singapore

ISBN: (数字)9781728150406

ISBN: (纸本)9781728150413

This paper reviews our recent work on two novel semiconductor devices built on silicon-on-insulator (SOI) substrate. The Z 2 -FET, which operates with feedback mechanism, has been demonstrated with extremely sharp switching behaviors and gate-controlled hysteresis. It has found applications in high performance memories, electrostatic discharge protection and photodetection. PISD utilizes the substrate of SOI for photon-electron conversion and senses the photoelectron in-situ without need of any additional device. It has been used as one-transistor active pixel sensor (1T-APS) which is more compact than conventional CMOS sensor.

关键词： Substrates Logic gates Random access memory Sensors Silicon-on-insulator Electrostatic discharges MOSFET

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Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation

Hamiltonian Path Based Mixed-Cell-Height Legalization for Ne...

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Design Automation Conference

作者： Jianli Chen Ziran Zhu Qinghai Liu Yimin Zhang Wenxing Zhu Yao-Wen Chang State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (数字)9781728110851

ISBN: (纸本)9781728158020

In modern circuit designs, standard cells are designed with different heights based on the power, area, and other characteristics to address various design requirements. For those cells with different heights, in particular, there are inter-cell diffusion steps if the diffusion heights of neighboring cells are different, called the neighbor diffusion effect (NDE) which has become critical in advanced technology nodes. In this paper, we present a Hamiltonian-path-based mixed-cell-height legalization algorithm for NDE mitigation. We first present a row assignment method considering both cell displacements and diffusion steps to assign cells to their desired rows that meet the power-rail alignment constraints. Then, we propose a Hamiltonian-path-based diffusion-step reduction method to effectively reduce the NDE violations while preserving the global placement solution. Particularly, we develop a 2-approximation algorithm to find a minimum weight Hamiltonian path connecting two vertices, and a 1.5-approximation algorithm to find a minimum weight Hamiltonian path with a specified end vertex. Finally, we present an NDE-aware legalization method with design compaction to resolve overlaps and NDE violations. Experimental results show that our algorithm can resolve all NDE violations without any area overhead in reasonable runtime.

关键词： Approximation algorithms Circuit synthesis Compaction Runtime Heuristic algorithms Standards Graph theory

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