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arXiv 2019年

作者： Liu, Chao Sun, Heming Chen, Jun'an Cheng, Zhengxue Takeuchi, Masaru Katto, Jiro Zeng, Xiaoyang Fan, Yibo State Key Lab of ASIC and System Fudan University Shanghai China Waseda Research Institute for Science and Engineering Waseda University Tokyo Japan

In this paper, a dual learning-based method in intra coding is introduced for PCS Grand Challenge. This method is mainly composed of two parts: intra prediction and reconstruction filtering. They use different network structures, the neural network-based intra prediction uses the full-connected network to predict the block while the neural network-based reconstruction filtering utilizes the convolutional networks. Different with the previous filtering works, we use a network with more powerful feature extraction capabilities in our reconstruction filtering network. And the filtering unit is the block-level so as to achieve a more accurate filtering compensation. To our best knowledge, among all the learning-based methods, this is the first attempt to combine two different networks in one application, and we achieve the state-of-the-art performance for AI configuration on the HEVC Test sequences. The experimental result shows that our method leads to significant BD-rate saving for provided 8 sequences compared to HM-16.20 baseline (average 10.24% and 3.57% bitrate reductions for all-intra and random-access coding, respectively). For HEVC test sequences, our model also achieved a 9.70% BD-rate saving compared to HM-16.20 baseline for all-intra configuration. Copyright © 2019, The Authors. All rights reserved.

关键词： Video signal processing

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Bayesian optimization approach for analog circuit synthesis using neural network

arXiv

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arXiv 2019年

作者： Zhang, Shuhan Lyu, Wenlong Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan State Key Lab of ASIC & System Microelectronics Department Fudan University China Department of Electrical Engineering University of Texas Dallas United States

Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N3), and the computation complexity of prediction is O(N2), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits. Copyright © 2019, The Authors. All rights reserved.

关键词： Deep neural networks

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Suppressing crosstalk in the photoelectron in-situ sensing device (PISD) by double SOI

Suppressing crosstalk in the photoelectron in-situ sensing d...

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International Conference on Ultimate Integration of Silicon, ULIS

作者： M. Arsalan Liu Jian A. Zaslavsky S. Cristoloveanu X. Zhang FY. Liu B. Li J. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Brown University Providence RI USA IMEP-LAHC INP-Grenoble/Minatec Grenoble France Institute of Microelectronics Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of SciencesBeijingChina100029

ISBN: (数字)9781728187655

ISBN: (纸本)9781728187662

In our previous work on silicon-on-insulator (SOI) photodetectors, we have used the deep-depletion effect in SOI substrates to construct the photoelectron in-situ sensing device (PISD). The PISD is a one-transistor active pixel sensor (1T-Aps) that is more compact than conventional CMOS sensors. In this work, we study the crosstalk between different pixels in the PISD, which is severe in a conventional SOI substrate. Through TCAD simulations, the use of a double SOI (DSOI) substrate is shown to suppress crosstalk between PISD pixels. The on extra buried oxide layer completely separates the substrate into two parts which shield the movements of charges across the adjacent cells. The impact of top Si thickness and buried oxide thickness is observed.

关键词： Semiconductor device modeling Simulation Crosstalk Silicon-on-insulator Silicon Sensors Substrates

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A wide range and high resolution two-step TDC for millimeter-wave band ADPLL

A wide range and high resolution two-step TDC for millimeter...

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International Conference on asic

作者： Jieyang Li Ting Yi Zhiliang Hong State Key Lab. of ASIC and System Fudan University Room 245 Microelectronic Building NO. 825 Zhangheng Rd Pudong District Shanghai China

A two-step time-to-digital converter operating at high frequency and acting as the Phase-Frequency Detector in millimeter-wave ADPLL is presented. Coarse TDC is to cover the input dynamic range and pass the sub-sampled residue to Fine TDC for more accurate quantization. A Vernier FTDC architecture based on two 11-stage ring delay chains has been proposed. A sense-amplifier based arbiter is applied in FTDC, which can still work even if the time difference between the data and clock rising edges is less than 50fs, further breaking the bottleneck of resolution. Besides, a new adaptive resetting mechanism is used for arbiters and ring oscillators in FTDC. Implemented in 28nm CMOS technology, simulation results show that this two-step TDC can achieve a resolution of 0.5ps and cover 10 bit input dynamic range, wide enough to process input signals with frequencies exceeding 10GHz. The simulated DNL and INL of TDC is 0.42LSB and 1.38 LSB, respectively.

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Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient

Fast QTMT Partition Decision Algorithm in VVC Intra Coding b...

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IEEE Visual Communications and Image Processing Conference

作者： Junan Chen Heming Sun Jiro Katto Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University China Waseda Research Institute for Science and Engineering Japan Faculty of Science and Engineering Waseda University Japan

Quadtree with nested multi-type tree (QTMT) partition structure in Versatile Video Coding (VVC) contributes to superior encoding performance compared to the basic quadtree (QT) structure in High Efficiency Video Coding (HEVC). However, the improvement of performance leads to an unavoidable increase of computational complexity. To achieve a balance between coding efficiency and compression quality, we propose a fast intra partition algorithm based on variance and gradient to solve the rectangular partition problem in VVC. First, further splitting of smooth areas is terminated. Then, QT partition is chosen depending on the gradient features extracted by Sobel operator. Finally, one partition from five possible QTMT partitions is directly chosen by computing the variance of variance of sub-CUs. The theoretical basis of our method is that a homogeneous area tends to be predicted with a larger coding unit (CU), and sub-parts of a split CU are prone to have different textures from each other. To our knowledge, this is the first attempt to apply traditional method to accelerating the rectangular partition problem in VVC intra prediction. Experimental results show that the proposed method can save aver-agely 53.17% encoding time with only 1.62% BDBR increase and 0.09dB BDPSNR loss compared to anchor VTM4.0.

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HRAE: Hardware-assisted Randomization against Adversarial Example Attacks

HRAE: Hardware-assisted Randomization against Adversarial Ex...

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Asian Test Symposium (ATS)

作者： Jiliang Zhang Shuang Peng Yupeng Hu Fei Peng Wei Hu Jinmei Lai Jing Ye Xiangqi Wang College of Computer Science and Electronic Engineering Hunan University Cyberspace Security Research Center Peng Cheng Lab Shenzheng China School of Cybersecurity Northwestern Polytechnical University State Key Laboratory of ASIC and System Fudan University SKL of CA ICT CAS UCAS Mathematics and Computational Science Hunan First Normal University

ISBN: (数字)9781728174679

ISBN: (纸本)9781728174686

With the rapid advancements of the artificial intelligence, machine learning, especially neural networks, have shown huge superiority over humans in image recognition, autonomous vehicles and medical diagnosis. However, its opacity and inexplicability provide many chances for malicious attackers. Recent researches have shown that neural networks are vulnerable to adversarial example (AE) attacks. In the testing stage, it fools the model by adding subtle perturbations to the original sample to misclassify the input, which poses a serious threat to safety-critical areas such as autonomous driving. In order to mitigate this threat, this paper proposes a hardware-assisted randomization method against AEs, where an approximate computing technique in hardware, voltage over-scaling (VOS), is used to randomize the training set of the model, then the processed data are used to generate multiple neural network models, finally multiple redundant models are used for the integrated classification and detection of the AEs. Various AE attacks on the proposed defense are evaluated to prove its effectiveness.

关键词： Training Perturbation methods Neural networks Data models Computational modeling Delays Robustness

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Erratum: Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage

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Journal of Instrumentation 2024年第10期19卷 E10001-E10001页

作者： Y. Li F. Liu B. Lu Z. Li S. Chen C. Zhang H. Zhu X. Yao J. Bu J. Wan Y. Xu S. Cristoloveanu B. Li J. Luo T. Ye Institute of Microelectronics of the Chinese Academy of Sciences 3 Beitucheng West Road Beijing 100029 China University of Chinese Academy of Sciences 19 A Yuquan Road Beijing 100049 China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of Sciences 3 Beitucheng West Road Beijing 100029 China State Key Laboratory of Particle Detection and Electronics of China 19 B Yuquan Road Beijing 100049 China Institute of High Energy Physics Chinese Academy of Science 19 B Yuquan Road Beijing 100049 China State key lab of ASIC and System Fudan University No. 825 Zhangheng Road Shanghai 200433 China College of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunication No. 9 Wenyuan Road Nanjing 210023 China Guangdong Greater Bay Area Institute of Integrated Circuit and System No. 136 Kaiyuan Avenue Guangzhou 510535 China

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A High Energy-Efficient Reconfigurable VLIW Symmetric Cryptographic Processor with Loop Buffer Structure and Chain Processing Mechanism

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Chinese Journal of Electronics 2017年第6期26卷 1161-1167页

作者： LI Wei ZENG Xiaoyang DAI Zibin NAN Longmei CHEN Tao MA Chao State Key Lab of ASIC and System Fudan University Institute of Information Science and Technology Zhengzhou

By exploring symmetric cryptographic data level and instruction-level parallelism, the reconfigurable processor architecture for symmetric ciphers is presented based on Very-long instruction word(VLIW) structure. The application-specific instruction-set system for symmetric ciphers is proposed. As for the same arithmetic operation of symmetric ciphers, eleven kinds of reconfigurable cryptographic arithmetic units are designed by the reconfigurable technology. As to the requirement of high energy-efficient design, the loop buffer structure for instruction fetching unit is proposed to reduce the power consumption significantly with the same frequency as conventional, meanwhile, the chain processing mechanism is proposed to improve the cryptographic throughput without any area overhead. It has been fabricated with 0.18μm CMOS technology. The result shows that the processor can work up to 200 MHz, and the fourteen kinds of cryptographic algorithms were mapped in the processor, the encryption throughput of AES, SNOW2.0 and SHA2 algorithm can achieve 1.19 Gbps, 1.05 Gbps, and 407 Mbps respectively.

关键词： Symmetric cipher Energy-efficient VLIW processor Loop buffer structure Chain processing mechanism Reconfigurable

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Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network

Efficient Performance Trade-off Modeling for Analog Circuit ...

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IEEE International Conference on Computer-Aided Design

作者： Zhengqi Gao Jun Tao Fan Yang Yangfeng Su Dian Zhou Xuan Zeng ASIC & System State Key Lab School of Microelectronics Fudan University Shanghai China School of Mathematical Sciences Fudan University Shanghai China University of Texas at Dallas Dallas USA

In this paper, we propose an efficient performance trade-off modeling method for analog circuit based on Bayesian Neural Network (BNN). First, we use a single BNN to simultaneously model multiple performances of interest (PoIs) of an analog circuit. This BNN model can be trained by using a novel automatic differential variational inference (ADVI) method with affordable computational cost. Next, the performance trade-off model can be extracted by embedding BNN into Bayesian optimization framework combined with a modified multi-objective evolutionary method. Since the correlations among different PoIs are implicitly encoded in the BNN model, the proposed method can capture the performance trade-off model efficiently and accurately. The numerical experiments demonstrate that compared to the state-of-the-art algorithms, the proposed method can achieve up to 2× runtime reduction without surrendering any accuracy.

关键词： Computational modeling Analog circuits Pareto optimization Integrated circuit modeling Bayes methods Neural networks

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An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis

arXiv

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arXiv 2019年

作者： Zhang, Shuhan Lyu, Wenlong Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan Hu, Xiangdong State Key Lab of ASIC & System Microelectronics Department Fudan University China Shanghai High Performance Integrated Circuit Design Center China University of Texas at Dallas Dallas United States

This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low- and high-fidelity black-box functions separately. The nonlinear map between the low-fidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low- and high-fidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect. Copyright © 2019, The Authors. All rights reserved.

关键词： Timing circuits

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