检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

736 篇 会议
74 篇 期刊文献

馆藏范围

810 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

501 篇 工学
- 301 篇 电子科学与技术（可...
- 164 篇 计算机科学与技术...
- 99 篇 信息与通信工程
- 93 篇 电气工程
- 93 篇 软件工程
- 69 篇 材料科学与工程（可...
- 43 篇 化学工程与技术
- 36 篇 仪器科学与技术
- 36 篇 控制科学与工程
- 34 篇 光学工程
- 31 篇 机械工程
- 19 篇 冶金工程
- 16 篇 动力工程及工程热...
- 11 篇 网络空间安全
- 10 篇 生物医学工程（可授...
- 7 篇 生物工程
- 5 篇 建筑学
- 5 篇 土木工程
200 篇 理学
- 93 篇 物理学
- 83 篇 数学
- 45 篇 化学
- 18 篇 统计学（可授理学、...
- 13 篇 系统科学
- 8 篇 生物学
30 篇 管理学
- 29 篇 管理科学与工程(可...
- 11 篇 工商管理
10 篇 军事学
- 10 篇 军队指挥学
8 篇 经济学
- 8 篇 应用经济学
4 篇 法学
- 4 篇 社会学
3 篇 医学
1 篇 农学
1 篇 艺术学

主题

28 篇 hardware
25 篇 clocks
22 篇 field programmab...
21 篇 throughput
21 篇 cmos technology
20 篇 application spec...
19 篇 abstracts
18 篇 logic gates
18 篇 random access me...
17 篇 computer archite...
17 篇 switches
15 篇 computational mo...
15 篇 silicon
14 篇 films
14 篇 decoding
13 篇 cmos integrated ...
13 篇 substrates
13 篇 voltage
13 篇 algorithm design...
13 篇 field programmab...

机构

115 篇 state key lab of...
96 篇 state key lab of...
58 篇 state key lab. o...
30 篇 state-key lab of...
23 篇 state key lab of...
19 篇 asic and system ...
19 篇 asic and system ...
16 篇 state key lab of...
15 篇 state-key lab. o...
15 篇 state key lab of...
14 篇 asic & system st...
13 篇 center for discr...
11 篇 state key lab of...
10 篇 state key lab. o...
9 篇 state key lab of...
8 篇 the state key la...
8 篇 department of mi...
7 篇 fudan university...
7 篇 school of microe...
6 篇 state key lab of...

作者

87 篇 xiaoyang zeng
44 篇 zeng xiaoyang
42 篇 xuan zeng
32 篇 xin-ping qu
29 篇 jianli chen
27 篇 jia zhou
27 篇 yibo fan
26 篇 jun yu
24 篇 dian zhou
22 篇 wei li
22 篇 jun han
22 篇 fan yang
22 篇 junyan ren
20 篇 yinyin lin
20 篇 zeng xuan
18 篇 chi nan
18 篇 yun chen
17 篇 kun wang
17 篇 lingli wang
16 篇 nan chi

语言

765 篇 英文
42 篇 中文
3 篇 其他

检索条件"机构=ASIC and System State-key Lab"

共 810 条记录，以下是211-220 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Sub-10 nm silicon FinFET devices on SOI substrate made by block copolymer lithography

Sub-10 nm silicon FinFET devices on SOI substrate made by bl...

引用

International Conference on Solid-state and Integrated Circuit Technology

作者： Dong-Xue Li Chien-Liang Chien Xinnian Wei Yanwei Huang Xin-Ping Qu Tzu-Hsuan Chang Shisheng Xiong School of Microelectronics State Key Lab of ASIC and System Fudan University Shanghai China Department of Electrical Engineering National Taiwan University Taipei School of Information Science and Technology Fudan University Shanghai China

Block copolymer (BCP) lithography as a low-cost and simple process emerges to become an important patterning technique in microelectronic manufacturing. In this work, self-assembly of a triblock copolymer was used to prepare silicon nanowire FinFET devices on the SOI substrate. The original pattern was formed on the block copolymer layer via self-assembly, and then transferred to the Si layer by dry etching that stops at the interface of Si and box oxide. The minimum critical dimension of the device can be as small as 8 nm, and the performance is extensively evaluated. This type of FinFET device shows high transconductance (g m ) 150 μS, signifies extremely low off current (I OFF ) ~50 pA, and high on/off current ratio (I ON /I OFF ) up to 3×10 6 .

关键词： Silicon FinFETs Self-assembly Substrates Silicon-on-insulator Lithography Nanoscale devices

来源：评论

学校读者我要写书评

暂无评论

Efficient Statistical Analysis for Correlated Rare Failure Events

Efficient Statistical Analysis for Correlated Rare Failure E...

引用

IEEE International Conference on Solid-state and Integrated Circuit Technology

作者： Jun Tao Zhengqi Gao Dian Zhou Xuan Zeng ASIC & System State Key Lab Dept. of Microelectronics Fudan University Shanghai China

To estimate the overall rare probability of correlated failure events for complex system containing a large number of replicated cells, we summarize two novel techniques in this paper. First, Asymptotic Probability Approximation (APA) method is introduced to capture the correlations among the failures of different cells by exploring a series of carefully defined partial failure events. Next, the entire system failure rate can be approximated by using a linear function of the total number of cells. Second, to further improve the estimation accuracy, we present the Asymptotic Probability Evaluation (APE) approach. The key idea of APE is to approximate the failure rate of the entire system by solving a set of nonlinear equations derived from a general analytical model. The numerical experiments demonstrate that APA and APE can accurately and efficiently estimates the overall failure rate of correlated rare failure events.

关键词： APA APE efficiently estimates

来源：评论

学校读者我要写书评

暂无评论

Parallel sparse LU decomposition using FPGA with an efficient cache architecture

Parallel sparse LU decomposition using FPGA with an efficien...

引用

International Conference on asic

作者： Xiang Ge Hengliang Zhu Fan Yang Lingli Wang Xuan Zeng State Key Lab of ASIC & System Fudan University Shanghai China

LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear equations. The complex data dependency makes it difficult to parallelize the LU decomposition. In this paper, an architecture with an efficient cache for parallel sparse LU decomposition using FPGA is proposed. The proposed architecture is based on the Gilbert-Peierls (G-P) algorithm. By using the elimination graph, we find the column dependency of the LU decomposition. It is thus possible to exploit the parallelism. Through a dependency table, a simple but efficient cache strategy and its corresponding architecture are proposed. The proposed cache strategy avoids the cache miss and reduces the size of cache used to store all the intermediate data on chip. The experiment demonstrates that, our design can achieve speedup of 2.85x-10.27x, compared with UMFPACK running on general purpose processors. The cache size can be reduced by 50.93% on average with the proposed cache strategy.

关键词： Field programmable gate arrays Computer architecture Sparse matrices system-on-chip Matrix decomposition Parallel processing Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

A High-Flexibility and Energy-Efficient Application-Specific Cryptography VLIW Processor for Symmetric Cipher Algorithms 13

A High-Flexibility and Energy-Efficient Application-Specific...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Wei Li Xiaoyang Zeng Longmei Nan Tao Chen Zibin Dai State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

In this paper, a high-flexibility and energy-efficien reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word(VLIW) structure. By analyzing basic operations and storage characteristics of symmetric ciphers, the application-specific instruction-set system for symmetric ciphers is proposed. Eleven kinds of reconfigurable cryptographic arithmetic units are designed to support different operation modes and parameters for symmetric ciphers. It has been fabricated with 0.18μm CMOS technology, the test results show tha the max frequency can reach 200 MHz. Ten kinds of block stream and hash ciphers were mapped in our processor And the encryption throughput of AES, IDEA, Grain128SNOW2.0 and SHA-2 algorithm can achieve 882Mbps449 Mbps, 60 Mbps, 840 Mbps, and 287 Mbps respectively Moreover, the energy efficiency of AES implementation is 0.47 nJ /bit. The result demonstrated that proposed processor outperforms other designs in terms of energy efficiency, throughput and flexibility.

关键词： A High-Flexibility and Energy-Efficient Application-Specific Cryptography VLIW Processor for Symmetric Cipher Algorithms

来源：评论

学校读者我要写书评

暂无评论

Study of DC sputtered SnO growth and its applications in thin film transistors 13

Study of DC sputtered SnO growth and its applications in thi...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Ji-Yu Feng Chun-Feng Hu Xin-Ping Qu State Key lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

In this work, p-type SnO thin films by DC sputtering at low temperature and TFT structures were fabricated. A probable process window of sputtering atmosphere of a mixture of Ar-O was found for SnO TFTs application. Fabricated-type SnO TFTs with I/Iof 5ⅹ103 and mobility of 0.17 cm/V·s on AlO dielectrics were fabricated. An unusual drain current shake in subthreshold field was found and more measurements and analysis should be carried out to explain this phenomenon.

关键词： SnO TFT Study of DC sputtered SnO growth and its applications in thin film transistors

来源：评论

学校读者我要写书评

暂无评论

The Research of Multistage Interconnection Structure Based on Crossbar 13

The Research of Multistage Interconnection Structure Based o...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Haiyuan Ni Wei Li Yingjian Yan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

To realize the high-speed performance of the processor, we need to research an efficient and flexible interconnection structure. In this paper, we propose a multistage interconnect structure based on Crossbar in the Coarse-Grained Reconfigurable Logic Array(CGRLA). Inner internet implements the connection of Functional operation unit flexibly and the outer internet implements the data transmission of different level of function units. Through the simulation verification, the results show that the structure we put up is better than similar design and there are some characteristics, such as small area, low occupancy rate of resources, high flexibility, high area transfer rate and so on, can effectively reduce the routing time in the algorithm implementation process, and improve the processing performance of the processor.

关键词： Interconnection structure Coarse-grained Reconfigurable Logic Array multistage interconnection network small area high flexibility

来源：评论

学校读者我要写书评

暂无评论

The Research of Loop Unrolling for Coarse-Grained Reconfigurable Block Encryption Array 13

The Research of Loop Unrolling for Coarse-Grained Reconfigur...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Yu-Hang Yang Wei Li Jin-Fu Xu Lu Liu State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Coarse-grained reconfigurable block encryption array（REBA） provides massively parallel computing resources but traditional mapping scheme does not develop the advantages of REBA. In this paper, aiming to improve the performance and resource efficiency of algorithm mapping, we research the structure of familiar block cipher algorithm, and propose the speed-up model based on loop unrolling and the modified strategy of unrolling in resource-constrained situation. Experimental results show that the proposed scheme develops the advantage of parallel resources that has 25-55 times higher throughput and 3-11 times higher throughput per unit of array area than the traditional scheme. Compared with other methods, our scheme has a higher performance-area ratio and smaller solving complexity.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

来源：评论

学校读者我要写书评

暂无评论

A Hardware Friendly Stereo Match Refinement Algorithm Using Disparity Gradient Based Region Growth Method 13

A Hardware Friendly Stereo Match Refinement Algorithm Using ...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Hanrui Wang Yize Jin Liming Wang Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Stereo Match is one of the key fields in computer vision. Although many dense two-frame stereo algorithms have been developed in this domain, few utilize cross check and disparity gradient based refinement method. This paper proposes:(1) Cross check method using two generated disparity maps based on left and right original images.(2) A novel occluded and low-texture region growth method based on disparity gradient.(3) Disparity voting method to reduce random error. These practical methods are hardware friendly and can notably improve match accuracy as well as lower the computational and space complexity. The proposed algorithm reaches the highest match accuracy for HR images among existing local methods, attesting to its outstanding effectiveness.

关键词： image A Hardware Friendly Stereo Match Refinement Algorithm Using Disparity Gradient Based Region Growth Method

来源：评论

学校读者我要写书评

暂无评论

Novel Hybrid Computing Architecture with Memristor-Based Processing-in-Memory for Data-Intensive Applications

Novel Hybrid Computing Architecture with Memristor-Based Pro...

引用

IEEE International Conference on Solid-state and Integrated Circuit Technology

作者： Xunming Zhang Quan Zhang Jianguo Yang Zedai Wangchen Ming'e Jing Mingyu Wang Xiaoyang Zeng Xiaoyong Xue Dept. of Electronics and Information Engineering Tongji University Shanghai China ASIC & System State Key Lab Fudan University Shanghai China

In this work, a novel hybrid computing architecture with memristor-based processing-in-memory (MPiM) is proposed to resolve the memory-wall issue for data-intensive applications. The datapath and control logic are redesigned to incorporate MPiM. Thus, some data can be processed in the memory array or the specific logic near the memory array. So the data to be transfered over the bus can be reduced considerably, saving power as well as improving the performance. Evaluations on data-intensive applications show reductions of 80% in energy consumption and 75% reduction in processing latency.

关键词： redesigned incorporate MPiM

来源：评论

学校读者我要写书评

暂无评论

Hardware Friendly Algorithm of HR Real Time Stereo Matching for Automatic Drive 13

Hardware Friendly Algorithm of HR Real Time Stereo Matching ...

引用

2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： Liming Wang Hanrui Wang Yize Jin Xiaoyang Zeng Yibo Fan State Key Lab of ASIC and System Fudan University

ISBN: (纸本)9781467397209

Stereo matching is a most challenging topic in artificial intelligence. Local algorithms are better than global ones with lower complexity and higher speed for HD real-time stereo matching. This paper proposes an optimized local stereo algorithm adaptive window disparity estimation with cross check(AWDE-CC). A region growth algorithm to fill bad pixels is also proposed which can bring an improvement of the performance in low texture regions efficiently. The average error rate of the generated disparity maps is approximately 8%.

关键词： Local stereo match adaptive window cross check region growth

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共81页 << < 18 19 20 21 22 23 24 25 26 27 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：