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IEEE ICCE-China Workshop (ICCE-China)

作者： Kunsong Zhu Lichao Zhang Zibin Dai Wei Li Department of Microelectronics Zhengzhou Institute of Information Science and Technology Zhengzhou China State Key Lab of ASIC and System Fudan University Shanghai China

ISBN: (纸本)9781509061945

With the popularity of Internet of Things technology in consumer electronic product, the security of data in these devices is becoming increasingly important. However, common encryption schemes are not well suited for these resource-constrained devices. To solve this problem, a low-cost SM4 implementation structure based on resource reutilization is proposed in this paper. The round function and key expansion use the core module in serial and all the round keys generated on-the-fly. Composite field S-box and barrel shifter allow the circuit area to be further reduced. key store & check module and CK generate module can improve the efficiency of decode mode. The result shows that only 2756 GE is used in our design on SMIC 0.18 um CMOS technology, and it can achieve 318 of FOM (Figure of Merit). Therefore, it is quite a good way to protect the security of data in consumer electronic product.

关键词： Encryption Decoding Consumer electronics Algorithm design and analysis Ciphers Conferences

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The Design of Digital Demodulator Based on Dynamic Threshold

The Design of Digital Demodulator Based on Dynamic Threshold

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2016 13th IEEE International Conference on Solid-state and Integrated Circuit Technology (ICSICT)

作者： ZHANG Xingxing LU Jicheng LI Xiayu YU Jun State Key Lab of ASIC & System Fudan University School of Microelectronics Fudan University Shanghai Fudan Microelectronics Group Co. Ltd.

In this paper,the influence of signal and noise on digital demodulator as well as the importance of a reasonable threshold are elaborated. A new method of threshold setting is presented, which is adjusted according to...

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Design of a high parallelism high throughput HSPA+ Turbo decoder 11

Design of a high parallelism high throughput HSPA+ Turbo dec...

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11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (asic), asicON 2015

作者： Cheng, Jieqiong Yang, Qingqing Zhou, Xiaofang State Key Lab of ASIC and System Fudan University Shanghai200433 China

ISBN: (纸本)9781479984831

Research in high throughput, high performance Turbo coding systems has an important significance for the development of modern wireless communication systems. This work presents a design of a high parallelism high throughput HSPA+ Turbo decoder in which a novel anti-contention structure named TMFDB is adopted to solve the memory contention problem more efficiently. The circuit is synthesized by Synopsys DC with TSMC LP 65nm technology, and the result shows that it can work in a maximum frequency of 465MHz, which means an throughput up to 792Mbps when the number of iteration is set to 5.5, and meet HSPA+'s throughput demands of 672Mbps. © 2015 IEEE.

关键词： Throughput

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A 0.45V 687pW low noise amplifier front-end with 1.73 NEF for energy-scavenging IoT sensors

A 0.45V 687pW low noise amplifier front-end with 1.73 NEF fo...

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IEEE International Wireless Symposium (IWS)

作者： Shuo Li Xiong Zhou Sanfeng Zhang Hailiang Yao Qiang Li Vahid Behravan Arun Natarajan Zhiliang Hong Patrick Y. Chiang State Key Laboratory of ASIC & System Fudan University Shanghai China Integrated Systems Lab University of Electronic Science and Technology of China Chengdu China School of EECS Oregon State University Corvallis OR USA

ISBN: (纸本)9781509006977

This paper presents a sub-nanowatt front-end amplifier for ultra-low-power wireless IoT sensor nodes. This chip consists of an instrumentation amplifier, a DC servo loop, a clock generator and a bias circuit. It is fully integrated, and therefore does not rely on any off-chip references. Fabricated in 65nm CMOS process, measurement results show that the amplifier system achieves 39dB gain and 0.1-130Hz bandwidth, sufficient for many low-frequency sensor interface applications. The measured power is 687pW for a 0.45V supply voltage, which when compared with previously published AFEs, is the only sub-nW low-noise amplifier.

关键词： Clocks Sensors Wireless sensor networks Wireless communication Voltage measurement Frequency measurement Gain measurement

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An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation

An efficient trajectory-based algorithm for model order redu...

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Asia and South Pacific Design Automation Conference

作者： Chenjie Yang Fan Yang Xuan Zeng Dian Zhou State Key Lab of ASIC & System Fudan University Shanghai P. R. China Department of Electrical Engineering University of Texas at Dallas Richardson TX U.S.A

ISBN: (纸本)9781467395700

Trajectory-based methods offer an effective methodology for generating the reduced-order models (ROMs) for nonlinear systems. These methods first sample on the state trajectories driven by the training inputs, then linearize and reduce the linearized systems around the sample points. However, these methods depend on an single global reduction subspace generated by combining all the projection subspaces of the sample points on the trajectories. In order to address this problem, a localized reduction technique has been proposed. This method weaves together a larger set of smaller localized ROMs for the trajectory samples. However, since these localized ROMs do not share the same coordinates, these localized ROMs cannot be interpolated to derive new ROMs. As a result, a large number of localized ROMs are needed to cover the necessary state space and guarantee adequate reduction accuracy. In this paper, we propose a new, efficient trajectory-based model order reduction algorithm for nonlinear systems via localized projection and global interpolation. We employ an efficient procedure to transform the smaller localized ROMs into a set of equivalent ROMs with nearly consistent global coordinate. The ROMs for the nonlinear systems are then obtained by globally interpolating the localized ROMs. Because we can perform interpolation between these localized ROMs, the required number of localized ROMs can be greatly reduced.

关键词： Read only memory Interpolation Nonlinear systems Mathematical model Trajectory Transforms Reduced order systems

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A high-throughput processor for dual-field elliptic curve cryptography

A high-throughput processor for dual-field elliptic curve cr...

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2015 International Conference on Information and Communications Technologies, ICT 2015

作者： Li, Wei Yi, Weibing Ma, Chao Yi, Suwen Yang, Xiaohui Dai, Zibin Institue of Information Science and Technology Zhengzhou450001 China State-Key lab of ASIC and System Fudan University Shanghai201203 China

ISBN: (纸本)9781849199940

In this paper, a mixture of VLIW and vector architecture of ECC processor is proposed to perform either prime field GF(p) operations or binary field GF(2m) operations for arbitrary prime numbers and irreducible polynomials. Besides, an application specific instruction set for ECC is presented to support parallel processing with VLIW instruction structure features and vector register addressing modes. After implemented in 65-nm CMOS process, our proposed 521-bit dual field elliptic curve cryptographic processor can perform scalar multiplication in 1.3 ms over GF(p521) and 0.94 ms over GF(2521). Our ECC processor chip is advantageous in terms of functionality, scalability, and performance.

关键词： Geometry

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An automated test framework for SRAM-based FPGA 11

An automated test framework for SRAM-based FPGA

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11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (asic), asicON 2015

作者： Xuemin, Lv Moucheng, Yang Xuegong, Zhou Lingli, Wang School of Economics and Management Ningbo University of Technology Ningbo315211 China State Key Lab of ASIC and System Fudan University Shanghai200433 China

ISBN: (纸本)9781479984831

An automated test framework for SRAM-based FPGA is presented. With the framework, test configurations of different categories can be partially or completely generated, and the tests be running using the generated configurations. Data driven design provides the test framework the flexibility of change the user interface and the command line arguments via software configuration files, without modifying the source code of the framework. Experimental results shows that the test framework handles the complicate test flow efficiently, and release the test engineer from the tedious testing work. © 2015 IEEE.

关键词： User interfaces

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A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation

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IEICE ELECTRONICS EXPRESS 2015年第11期12卷 20150368-20150368页

作者： Su, Yuan Ye, Fan Ren, Junyan Fudan Univ State Key Lab ASIC & System Shanghai 201203 Peoples R China

This paper presents a high power-efficient low voltage differential signaling (LVDS) output driver with adjustable feed-forward capacitor compensation. Compared to conventional LVDS output driver, the proposed output driver helps to significantly reduce the requirement of driving capability of pre-driver by increasing the rising and falling time of outputs. In addition, its output swing is adjustable based on different loadings. The proposed LVDS output driver consumes 3.04 mW with a transmission data rate of 6 Gb/s, achieving a power efficiency of 0.51 mW/Gb/s. This output driver circuit is implemented in a 65 nm CMOS process with a core area of 0.025 mm(2).

关键词： high power-efficient LVDS output driver pre-driver adjustable feed-forward capacitor compensation

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An inclusive fault model for Network-on-Chip

An inclusive fault model for Network-on-Chip

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International Conference on asic

作者： Yi He Gensheng Chen State Key Lab of ASIC and System Fudan University

In this paper, we propose an inclusive NoC fault model incorporating both high-level abstraction and hardware structure. In high-level abstraction domain, we point out the deficiency of existing fault model as well as simulation procedure, and categorize faults according to their behavior on channel dependency graph CDG. We also introduce connectivity graph CG to identify connection break that faults might incur. In hardware structure domain, we include hardware faults with diverse granularities, and match each hardware fault to corresponding high-level abstraction fault. The fault model we propose shows convincing integrity, and brings more prospects to NoC fault handling.

关键词： Circuit faults Hardware Routing Fault tolerance Fault tolerant systems Integrated circuit modeling Topology

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A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS

A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase inter...

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IEEE MTT-S International Microwave Symposium, IMS 2015

作者： Ma, Shunli Manoj, Sai Yu, Hao Ren, Junyan Weerasekera, Roshan State Key Lab of ASIC and System Fudan University Shanghai200433 China School of EEE Nanyang Technological University Singapore639798 Singapore Institue of Microelectronics ASTAR Singapore

ISBN: (纸本)9781479982752

A full-rate energy-efficient forwarded-clock (FC) receiver is demonstrated in this paper. A current sampler with continuous-time equalization is realized with 20 GHz bandwidth in sampling for data recovery. Moreover, a phase interpolator is introduced to generate sampling clock with deskew for data recovery. The testing chip was fabricated in 65 nm CMOS process in area of 0.16 mm2. Measurement shows that the FC receiver can achieve a data-rate up to 9.8 Gbps and power consumption is 6.5 mW. © 2015 IEEE.

关键词： Clocks

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