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2013 IEEE 10th International Conference on asic, asicON 2013

作者： Yang, Jianguo Meng, Ying Xue, Xiaoyong Huang, R. Zhou, Q.T. Wu, J.G. Lin, Yinyin ASIC and System State Key Lab Fudan University Shanghai 201203 China SOC Technology Development Center Semiconductor Manufacturing International Corp Shanghai 201203 China

ISBN: (纸本)9781467364157

A 2-Mb resistive random access memory (ReRAM) is demonstrated in 0.13-um CMOS logic process. The paper describes the cell, chip architecture, and circuit techniques to ReRAM design;The 2-Mb ReRAM chip features three circuit technologies to improve the memory yield and performance: 1) for a better endurance and resistance distribution a ramped current pulse write driver (RCPWD) circuit is designed, 2) considering process variation and verify used, a programmable reference sense amplifier (PRSA) for stable read operation is designed, and 3) for improving the yield and reliability for some special application, a double error correction codes (DEC) circuit is introduced for yield requirement of high reliability applications. © 2013 IEEE.

关键词： Timing circuits

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An efficient routing scheme for irregular mesh NoCs

An efficient routing scheme for irregular mesh NoCs

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4th IEEE International Conference on Electronics Information and Emergency Communication, ICEIEC 2013

作者： Xiao, Qingli Fu, Hongzhou Zheng, Lu Zhang, Dexue College of Information Science and Engineering Shandong University of Science and Technology Qingdao 266590 China State-Key Lab. of ASIC and System Fudan University Shanghai 200240 China

ISBN: (纸本)9781467349314

Topological structure is an important part of the design of network on chip systems. The majority of current NoC architectures employ mesh topology, but at some practical application, NoC systems often integrate a number of heterogeneous blocks, or some fabrication faults, reliability issues, may lead to the need of irregular topologies. Consequently, simplistic routing techniques such as XY scheme can not be employed in irregular topologies. This paper presents an efficient specific routing scheme for the irregular mesh network which can be guaranteed for the connection in irregular topologies. This paper applies routing tables (RT) to realize the algorithm and use OVP (Open Virtual Platforms)+ TLM (Transaction Level Modeling)+systemC to create a virtual platform, achieving a 16 x16 irregular mesh topology of heterogeneous systems. Finally the routing scheme is applied to test specific real application network instances, and the result shows its connectivity and efficiency. © 2013 IEEE.

关键词： Network-on-chip

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A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder

A highly pipelined VLSI architecture for all modes and block...

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International Conference on asic

作者： Cong Liu Weiwei Shen Tianlong Ma Yibo Fan Xiaoyang Zeng State Key Lab of ASIC and System Fudan University Shanghai China

The adoption of 35 prediction modes and quad-tree structure in intra coding of High Efficiency Video Coding (HEVC) significantly improves the coding efficiency. In this paper, a highly pipelined 16-pixel parallel VLSI architecture of intra prediction in HEVC encoder is proposed, supporting all prediction modes and all block sizes. Original pixels are used to help to decide prediction mode and block partition in the premise of negligible PSNR degradation, and a universal predictor is presented. In order to reduce internal buffers when scanning full-mode and full-size predictions in encoder, post-order traversal is applied to the quad-tree structure blocks. It takes 8967 cycles to complete the intra prediction of a whole 32×32 treeblock, including prediction and the decision of mode and block partition. This design is synthesized with TSMC 65nm CMOS technology. It can run at 600 MHz, supporting real-time encoding of 1080P@30fps video sequence.

关键词： Video coding Computer architecture Engines Very large scale integration Standards Hardware Throughput

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An ultra low-power and area-efficient baseband processor for WBAN transmitter

An ultra low-power and area-efficient baseband processor for...

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Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA)

作者： Mengyuan Chen Jun Han Dabin Fang Yao Zou Xiaoyang Zeng State-Key Lab of ASIC and System Fudan University Shanghai China

The IEEE 802.15.6-2012 standard optimized for short-range/low power purpose for WBAN applications has been approved recently. Based on the standard, this paper proposes the hardware implementation of the baseband transmitter for the first time. In our design, the physical layer (PHY) employs narrowband(NB) PHY in the standard and DPSK Modulator is optimized by employing CSD-coded (canonical signed digit) filters for low power and area-efficiency consideration. Clock gating is also implemented to cut the dynamic power in the idle state. Implemented in 130nm CMOS technology, the least total power dissipation of the transmitter is only 69.5uW at 151.8kbps and 1.0V supply in the Medical Implant Communication Service (MICS) band. In addition, The power consumption of the PHY module under different frequency bands and different data rates is investigated. The minimum energy-per-bit is only 10.1pJ/bit at 971.4kbps indicating that our PHY module is more energy-efficient than previous works.

关键词： Finite impulse response filters Baseband IEEE 802.15 Standards Differential phase shift keying Power demand

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A hardware-efficient variable-length FFT processor for low-power applications

A hardware-efficient variable-length FFT processor for low-p...

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Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA)

作者： Yifan Bo Renfeng Dou Jun Han Xiaoyang Zeng State-Key Lab of ASIC and System Fudan University Shanghai China

The fast Fourier transformation (FFT) is a key operation in digital signal processing (DSP) systems and has been studied intensively to improve the performance. Nowadays, embedded DSP systems require low energy consumption to prolong the life cycle, which raises stringent power limitation for FFT processing. Meanwhile, sufficient signal-to-quantization-noise ratio (SQNR) is a basic requirement in these systems. In this paper, a modified data scaling scheme as well as trounding method is employed to improve the SQNR performance. Therefore word-length can be reduced and energy is saved accordingly. Memory-based architecture is chosen to support variable-length FFT processing. Also, constant multiplier array is introduced in the datapath to reduce the power dissipation with a slight increase of area. The proposed processor can perform 64-8192-point FFT processing. The core area is 2.29 mm 2 and the power consumption is 67.9 mW at 100MHz. Besides, the SQNR of 55.4 dB and 33.3 dB are achieved for 64-point and 8192-point FFT respectively.

关键词： Arrays Energy consumption Digital signal processing Power demand Algorithm design and analysis Generators

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Positionable Wearable Fall Detection system for Elderly Assisted Living Applications

Positionable Wearable Fall Detection System for Elderly Assi...

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International Conference on asic

作者： Jie Cheng Yun Chen Wenxu Bao YuanZhou Hu Na Ding Xiaoyang Zeng The State-Key Lab of ASIC and System Fudan University Shanghai China

Along with the degradation of the body function, the elderly are more likely to fall accidentally. And if they don't get timely and effective help, severe consequences may take place, even to death. Traditional medical monitoring equipment are bulk and not convenient to carry, difficult to achieve real-time monitoring of anytime and anywhere. This article designs a positionable wearable fall detection system based on GSM, GPS and ZigBee, using tri-axis acceleration as monitoring objects, transmitted by ZigBee, positioned by GPS, using GSM to send position and alarm short messages, fall action judged by PC using a fall detection algorithm which can distinguish falling down and daily activities.

关键词： GSM GPS ZigBee

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A Turbo Decoder Implementation for LTE Downlink Mapped on a Multi-Core Processor Platform

A Turbo Decoder Implementation for LTE Downlink Mapped on a ...

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International Conference on asic

作者： Qing Zhang Xueqiu Yu Zhiyi Yu Xiaoyang Zeng State Key Lab of ASIC and System Fudan University Shanghai P.R. China State Key Lab of ASIC and System Fudan University Shanghai 201203 China

This paper presents an implementation of turbo decoder in LTE downlink system on a multi-core processor platform. Turbo code, also called Parallel Concatenated Convolutional Code (PCCC) is used for LTE system [1] for its good error correcting ability and anti-interference ability [2]. As the wireless communication is developing constantly, it turns to be more difficult for asic baseband processing solutions to adapt the rapidly changing communication standards. The multi-core processor platform, a mesh array of SIMD cores, is well suited for wireless communication applications due to its programmability and re-configurability. We realize a turbo decoder with the throughput of 46Mbps by deeply excavating the task-level pipelining and data-level parallelism on multi-core processor platform.

关键词： LTE SIMD PCCC

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A fast 8×8 IDCT algorithm for HEVC

A fast 8×8 IDCT algorithm for HEVC

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International Conference on asic

作者： Tianlong Ma Cong Liu Yibo Fan Xiaoyang Zeng State Key Lab of ASIC & System Fudan University Shanghai China

As an approximation to the Discrete Cosine Transform (DCT), Integer Cosine Transform (ICT) is widely used in latest video coding standards, such as H.264/AVC, VC-1 and AVS. High Efficiency Video Coding (HEVC), the next generation of video compression standard, adopts 4/8/16/32 integer transform. Since the size of matrices themselves and the numerical magnitude of matrix elements are very large, HEVC transform suffers from huge computational complexity. To alleviate this problem, we proposed a fast algorithm for order-8 integer transform for HEVC. This algorithm has 66% less multiplications and 46% less additions than direct method and saves 60% area for hardware implementation. It is illustrated by signal-flow graph, which is easy to be translated to hardware or software implementation.

关键词： Discrete cosine transforms Matrix decomposition Hardware Video coding Algorithm design and analysis Standards

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Experimental demonstration for 40-km fiber and 2-m wireless transmission of 4-Gb/s OOK signals at 100-GHz carrier

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Chinese Optics Letters 2013年第2期11卷 24-26页

作者：汤禅娟李荣玲邵宇丰迟楠余建军董泽 G. K. Chang State Key Lab of ASIC and System Department of Communication Science and EngineeringFudan University The School of ECE Georgia Insititute of TechnologyAtlantaGA 30332USA

We experimentally demonstrate a 4-Gb/s radio-over-fiber （RoF） system with 40-kin fiber and 2-m wireless distance downstream at 100-GHz carrier. To the best of our knowledge, this is for the first time in China to realize optical wireless link at 100 GHz. In this letter, simple intensity modulator with direct detector （IM-DD） modulation is employed and optical power penalty afZer 40-kin single mode fiber （SMF）-28 and 2-m air link is 3.2 dB with bit-error-rate （BER） at 1 × 10- 9.

关键词： OOK RoF Experimental demonstration for 40-km fiber and 2-m wireless transmission of 4-Gb/s OOK signals at 100-GHz carrier

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A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique

A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Mi...

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International Conference on asic

作者： Yongzhen Chen Chixiao Chen Qiang Zhang Fan Ye Junyan Ren State-Key Lab of ASIC and System Fudan University Shanghai China

A CMOS fully differential high gain-bandwidth (GBW) operational amplifier applied in a sample-and-hold (S&H) circuit is presented in the paper. High bandwidth and phase margin of the amplifier are obtained by combining two compensation techniques: Miller compensation and Feedforward compensation. In addition, in order to achieve a high gain, the gain-boosting technique is employed. The circuit is designed in SMIC 65 nm process consuming 47.25 mW at a 1.2 V power supply and is suitable for 12-bit 200-MS/s pipelined ADC applications. At 200 MS/s, the S&H circuit achieves 77.68 dB SNDR for an input of 92.38 MHz.

关键词： Capacitors Transistors Feedforward neural networks Clocks Time-frequency analysis Poles and zeros CMOS integrated circuits

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