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检索条件"机构=ASIC and System State-key Lab"

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Compact and portable chemiluminescence detector for glucose

Compact and portable chemiluminescence detector for glucose

引用

International Conference on asic

作者： Kaidi Zhang Guowei Tao Xiangyu Zeng Wenjie Sheng Jia Zhou ASIC and System State Key Lab Fudan University Shanghai China

A compact chemiluminescence detector for glucose measurement based on a single planar transparent EWOD (electrowetting-on-dielectrics) device is designed and manufactured. Its sensitivity can be as high as 0.12V/μM, and it has a large detection range from 1μM to 20mM, and a low detection limit of 1μM. Such a detector demonstrates its potential as a portable immuno-detector with prompt response and low cost measurement compared with expensive and bulky traditional instruments.

关键词： Sugar Detectors Sensitivity Fluorescence Biosensors Distance measurement Electrodes

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Low-Power High-Yield SRAM Design with VSS Adaptive Boosting and BL Capacitance Variation Sensing

Low-Power High-Yield SRAM Design with VSS Adaptive Boosting ...

引用

International Conference on asic

作者： Ningxi Liu Yu Jiang Qing Dong Hui Li Xinyi Hu Yinyin Lin ASIC and System State Key Lab Fudan University Shanghai China

Adaptive VSS boosting with process variation compensation is proposed to reduce the standby leakage by 6X at room temperature and improves the write static noise margin. The N-pulse read assist circuit enables higher read stability and faster read speed. The systematic BL capacitance variation is detected, and a proper WL voltage is generated to mitigate the BL discharging speed variation by 20%.

关键词： Low power High yield Speed variation

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Simulation design for continuous separating and 3D focusing of particles based on inertial microfluidics

Simulation design for continuous separating and 3D focusing ...

引用

International Conference on asic

作者： Jian Li Xiangyu Zeng Jia Zhou ASIC and System State Key Lab Fudan University Shanghai China

This paper proposed a novel single-layer planar design of a microfluidic chip which utilizes inertial forces to realize continuous separating and three-dimensional (3D) focusing of particles. The theories of inertial microfluidics were analyzed and numerical simulation with COMSOL Multi-physics was verified by reported work. The results showed that both 3D focusing and separating of particles with a diameter of 1.0 μm and 9.9μm were obtained by changing the flow rates of inlets. The novel microfluidic design was robust, simple to perform and could easily be manufactured for laboratory and biomedical applications.

关键词： Focusing Three-dimensional displays Microfluidics Fluids Computational modeling Numerical models Data models

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The annealing effect of chemical vapor deposited graphene

The annealing effect of chemical vapor deposited graphene

引用

International Conference on asic

作者： Y. L. Shen P. Zhou L. H. Wang Q. Q. Sun Q. Q. Tao P. F. Wang S. J. Ding D. W. Zhang ASIC & System State Key Lab Fudan University Shanghai China

Chemical vapor deposited (CVD) graphene is one of the most widely-used methods to get large-area graphene. However, both CVD fabrication process and necessary transfer process will introduce a lot of defects. Therefore, reducing the defects in CVD graphene is a critical problem. In this work, we report the annealing effect to reduce the defects in graphene fabricated by CVD and transferred to Si/SiO 2 substrate. We annealed the CVD samples at five different temperatures in N 2 for 30 s. The Raman spectroscopy shows the defects can be reduced in the range of 200°C to 600°C. Atomic force microscopy (AFM) also indicates a much smoother surface can be reached below 600°C. When the annealing temperature above 800°C, the average carbon-carbon distance increases with the temperature. This will lead to a larger corrugation which is one kind of defects. Thermal expansion generated by high temperature will also damage the graphene lattice structure and therefore produces more disorders.

关键词： Graphene Annealing Substrates Silicon Surface morphology Lattices Films

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A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder asic for 3GPP-LTE and WiMAX systems in 65nm CMOS

A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC...

引用

IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Xubin Chen Yun Chen Yi Li Yuebin Huang Xiaoyang Zeng State Key Lab. of ASIC and System Fudan University Shanghai China

This paper presents a unified parallel radix-16 turbo decoder asic for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the asic attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.

关键词： Decoding Measurement WiMAX Throughput Application specific integrated circuits Parallel processing Turbo codes

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A 20 Gb/s Limiting Amplifier in 65nm CMOS technology

A 20 Gb/s Limiting Amplifier in 65nm CMOS technology

引用

International Conference on asic

作者： Rui He Jianfei Xu Na Yan Min Hao State Key Lab. of ASIC and System Fudan University Shanghai China

This paper presents a 20Gb/s Limiting Amplifier (LA) with the active interleaving feedback technique both to broaden the bandwidth and achieve flatness response. The LA includes an input match and DC offset cancellation (DCOC), a four-stage 3rd order amplifier core and an output buffer for test. Simulated in the 65nm CMOS technology, the LA exhibits a voltage gain of 38.5dB, a 3-dB bandwidth of 18GHz and an integrated input noise of 0.56mV with the area of only 0.45 × 0.25 mm 2 . The chip excluding buffer is supplied by 1.2V VDD and consumes DC power of 61mW.

关键词： Bandwidth Limiting CMOS integrated circuits Noise Gain CMOS technology Resistors

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A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks

A hybrid router combining circuit switching and packet switc...

引用

International Conference on asic

作者： Jie Lin Wei Zhou Zhiyi Yu Xiaoyang Zeng State Key Lab of ASIC and System Fudan University Shanghai P.R. China

In this paper, we propose a hybrid router which combines circuit switching and packet switching with virtual channels for on-chip networks in order to efficiently transfer streaming and best-effort traffics in specific applications. Time Division Multiplexing (TDM) technique and clock-gating scheme are used to take the benefits from the flexibility and throughput advantage of packet-switched router and superior power efficiency performance of circuit-switching. Synthesis and simulation results show that the proposed router has a gain of optimization in latency and average power consumption compared to either of the routers with single switching technique, with a slight growth of 6.8% in area overhead, while the virtual channels increase the network bandwidth by 26%.

关键词： Switching circuits Switches Clocks Packet switching Hybrid power systems Power demand Throughput

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H.264 video parallel decoder on a 24-core processor

H.264 video parallel decoder on a 24-core processor

引用

International Conference on asic

作者： Shikai Zhu Zheng Yu Shile Cui Zhiyi Yu Xiaoyang Zeng State Key Lab of ASIC and System Fudan University Shanghai P. R. China

This paper presents an implementation of H.264 decoder on a 24-core processor. H.264 provides many new features that require complex computations compared to the previous video coding standards, thus introduces great challenges to implement it efficiently. Multiprocessor emerges as a good solution because it provides high parallelism rather than high clock frequency to improve the system performance energy efficiently. By utilizing hardware accelerators and different levels of parallelism mechanism including function-level parallelism, data-level parallelism and thread-level parallelism, our proposed H.264 decoder shows a throughput of 58fps@720p at 800MHz with 780mW power dissipation.

关键词： Decoding Entropy Multicore processing Pipelines Parallel processing Power dissipation Throughput

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A new channel emulator for low voltage broadband power line communication

A new channel emulator for low voltage broadband power line ...

引用

International Conference on asic

作者： Yan Zhao Xiaofang Zhou Chao Lu State key lab of ASIC and System Fudan University Shanghai China ASEIT Co. Ltd Shanghai China

The design and testing of high speed powerline communication systems requires an efficient channel emulator. On the basis of low-voltage broadband PLC, with analysis of existing modeling and simulators, implementation of channel and noise models are discussed, and a flexible, easy configurable, practical and circuit area efficient channel simulator is presented, implemented and verified on FPGA.

关键词： Decision support systems

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High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer

High-speed and low-power 2.5D I/O circuits for memory-logic-...

引用

2013 IEEE International 3D systems Integration Conference, 3DIC 2013

作者： Wang, Jiacheng Ma, Shunli Manoj, P. D. Sai Yu, Mingbin Weerasekera, Roshan Yu, Hao ERI at N Interdisciplinary Graduate School Nanyang Technological University Singapore Singapore State Key Lab. of ASIC and System Fudan Univerisy China School of EEE Nanyang Technological Univerisy Singapore 639798 Singapore Institute of Microelectronics A STAR Singapore Singapore

ISBN: (纸本)9781467364843

In this paper, two high-speed and low-power I/O circuits are developed using through-silicon-interposer (TSI) for 2.5D integration of multi-core processor and memory in 65nm CMOS process. For a 3mm TSI interconnection of transmission line (T-line), the first I/O circuit is a low-voltage-differential- signal (LVDS) buffer and the second one is a current-mode-logic (CML) buffer. To compensate the high-frequency loss from T-line, a pre-emphasis circuit is deployed in the LVDS buffer, and a wide-band inductor-matching is deployed in the CML buffer. Based on the post layout simulation results, the LVDS buffer can achieve 360mV peak-to-peak differential output signal swing and 563fs cycle-to-cycle jitter with 10Gb/s bandwidth and 4.8mW power consumption. The CML buffer can achieve 240mV peak-to-peak differential output signal swing and 453fs jitter with 12.8Gb/s data-rate and 1.6mA current consumption under 0.6V ultra low-power supply. © 2013 IEEE.

关键词： Timing circuits

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