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A fully programmable reed-solomon decoder on a multi-core processor platform

A fully programmable reed-solomon decoder on a multi-core pr...

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作者： Huang, Bei You, Kaidi Chen, Yun Yu, Zhiyi Zeng, Xiaoyang State Key Lab of ASIC and System Fudan University China

Reed-Solomon (RS) codes are widely used in digital communication and storage systems. Unlike usual VLSI approaches, this paper presents a high throughput fully programmable Reed-Solomon decoder on a multi-core processor. The multi-core processor platform is a 2-Dimension mesh array of Single Instruction Multiple Data (SIMD) cores, and it is well suited for digital communication applications. By fully extracting the parallelizable operations of the RS decoding process, we propose multiple optimization techniques to improve system throughput, including: task level parallelism on different cores, data level parallelism on each SIMD core, minimizing memory access, and route length minimized task mapping techniques. For RS(255, 239, 8), experimental results show that our 12-core implementation achieve a throughput of 4.35 Gbps, which is much better than several other published implementations. From the results, it is predictable that the throughput is linear with the number of cores by our approach. Copyright © 2012 The Institute of Electronics, Information and Communication Engineers.

关键词： Parallel processing systems

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MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support

MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip s...

引用

International Conference on asic

作者： Dexue Zhang Xiaoyang Zeng Zongyan Wang Weike Wang Xinhua Chen State Key Lab. of ASIC & System Fudan University Shanghai China College of Information Science and Engineering Shandong University of Science and Technology Qingdao China Qingdao ShanHai Microelectronics Co. Ltd. Qingdao China

Many-core SoC (MCSoC) design is one of chip design trends and challenges. Modeling and simulation for large scale MCSoC design is the key to get it right the first time. NoC is the most important component of future MCSoC. A novel modeling tool, MCVP-NoC (Many-Core Virtual Platform with Networks-on-Chip support) was designed for large scale MCSoC modeling, and can be used in design space exploration, early software development and system verification. MCVP-NoC was built on systemC, OVP(Open Virtual Platform) and TLM2.0, integrated with Orion2.0 for power and area estimation. MCVP-NoC can run real software code, and can be used to evaluate the performance of the MCSoC design under real application load.

关键词： Decoding Software Computer architecture Analytical models system-on-chip Estimation Nickel

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An efficient packing algorithm based on constraint satisfaction problem technique

An efficient packing algorithm based on constraint satisfact...

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8th Southern Programmable Logic Conference, SPL 2012

作者： Yang, M. Tong, Jiarong State Key Lab. of ASIC and System Fudan University Shanghai China

ISBN: (纸本)9781467301862

In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited number of patterns, which can implement all functionalities of FPGA CLB logic. All the patterns are pre-designed and known as reference circuits. The proposed algorithm then matches the reference circuits from the given user logic circuit using specific constraints. Due to complex architecture of FPGA, to enumerate all the reference circuits in a fine-grain manner is impractical. Consequently, coarse-grain manner is adapted in the paper to overcome this problem. The experimental results show that the proposed algorithm achieves comparable performance in area and speed compared with literatures. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards

A unified 4/8/16/32-point integer IDCT architecture for mult...

引用

2012 13th IEEE International Conference on Multimedia and Expo, ICME 2012

作者： Shen, Sha Shen, Weiwei Fan, Yibo Zeng, Xiaoyang State Key Lab. of ASIC and System Fudan University Shanghai China

ISBN: (纸本)9781467316590

4 or 8-point IDCT are widely used in traditional video coding standards. However larger size (16/32-point) IDCT has been proposed in the next generation video standard such as HEVC. To fulfill this requirement, this work proposes a fast computational algorithm of large size integer IDCT. A unified VLSI architecture for 4/8/16/32-point integer IDCT is also proposed accordingly. It can support the following video standards: MPEG-2/4, H.264, AVS, VC-1 and HEVC. Multiplier less MCM (Multiple Constant Multiplication) is used for 4/8-point IDCT. The regular multipliers and sharing technique are used for 16/32-point IDCT. The transpose memory uses SRAM instead of the traditional register array in order to further reduce the hardware overhead. It can support real-time decoding of 4Kx2K (4096x2048) 30fps video sequence at 191MHz working frequency, with 93K gate count and 18944-bit SRAM. We suggest a normalized criterion called design efficiency to compare with previous works. It shows that this design is 31% more efficient than previous work. © 2012 IEEE.

关键词： Static random access storage

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The intrinsic coercive field for P(VDF-TrFE) thin-films with different thicknesses

The intrinsic coercive field for P(VDF-TrFE) thin-films with...

引用

International Symposium on Integrated Functionalities, ISIF 2011

作者： Liu, X.B. Jiang, A.Q. Tang, T.A. State Key Lab. of ASIC and System Fudan University Shanghai 200433 China

Generally, the organic ferroelectric P(VDF-TrFE) thin film is partially crystallized with a mixture of ferroelectric crystallites, non-crystalline molecules, and additional non-ferroelectric crystallites, e.g., Trifluoroethylene, in the copolymers. Therefore, it is almost impossible for the domains to switch under a normal field without incurring of charge injection across these non-ferroelectric phases. In this paper, we use an equivalent-circuit description of the film consisting of a non-ferroelectric layer in series with a ferroelectric layer. Based on the polynomial fitting of polarization switching/nonswitching results, we extract the intrinsic coercive field across the ferroelectric layer in the films with different thicknesses. Copyright © Taylor & Francis Group, LLC.

关键词： Equivalent circuits

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Mixed-signal system verification by systemC/systemC-AMS and HSIM-VCS in near field communication tag design

Mixed-signal system verification by SystemC/SystemC-AMS and ...

引用

International Conference on asic

作者： Zhaori Bi Wei Li Dian Zhou Xuan Zeng Sheng-Guo Wang Eric Jonsson School The University of Texas at Dallas Richardson U.S.A. State Key Lab. of ASIC & System Fudan University Shanghai China College of Engineering University of North Carolina at Charlotte Charlotte NC U.S.A.

Traditional circuit description languages such as SPICE, VHDL, and Verilog have limited capability of designing and verifying large scale mixed-signal systems, because they can only deal with analog or digital circuits and lack of flexibility of modeling complicated mixed-signal stimulus. This paper presents a verification method combining systemC/systemC-AMS and HSIM-VCS verification platforms to design a Near Field Communication (NFC) tag and verify its function under certain noise conditions.

关键词： Noise Modulation Integrated circuit modeling Clocks Load modeling Educational institutions Decoding

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The effect of H2O2 and ammonia sulfate on the CMP of molybdenum

The effect of H2O2 and ammonia sulfate on the CMP of molybde...

引用

2012 International Conference on Planarization/CMP Technology, ICPT 2012

作者： Chen, Fei Zeng, Xu Xu, Jing-Bo Lu, Hai-Sheng Qu, Xin-Ping State key lab of ASIC and System Department of Microelectronics Fudan University Shanghai200433 China

ISBN: (纸本)9783800734528

The chemical mechanical polishing (CMP) of Molybdenum (Mo) using hydrogen peroxide based alkaline solution was investigated. The effects of pH value and the H2O2 concentration on the Mo polishing were studied. The static etching rate (SER) and polishing rate (PR) were much higher in the alkaline solution and H2O2 can greatly enhance both SER and PR of Mo. It is found that in the presence of AS, not only the PR of Mo increased, but also the ratio of PR to SER of Mo was increased. According to the electrochemical measurements and the X-ray photoelectron spectroscopy results, it is proposed that, AS can react with MoO42- to form soluble ammonium molybdate to promote the removal of Mo. © ICPT 2012 - International Conference on Planarization/CMP Technology, Proceedings. All rights reserved.

关键词： Hydrogen peroxide

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An Efficient Routing Scheme for Irregular Mesh NoCs

An Efficient Routing Scheme for Irregular Mesh NoCs

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2013 IEEE 4th International Conference on Electronics Information and Emergency Communication

作者： Qingli Xiao Hongzhou Fu Lu Zheng Dexue Zhang College of Information Science and Engineering Shandong University of Science and Technology State-Key Lab. of ASIC and System Fudan University

ISBN: (纸本)9781467349345

Topological structure is an important part of the design of network on chip systems. The majority of current NoC architectures employ mesh topology, but at some practical application, NoC systems often integrate a number of heterogeneous blocks, or some fabrication faults, reliability issues, may lead to the need of irregular topologies. Consequently, simplistic routing techniques such as XY scheme can not be employed in irregular topologies. This paper presents an efficient specific routing scheme for the irregular mesh network which can be guaranteed for the connection in irregular topologies. This paper applies routing tables (RT) to realize the algorithm and use OVP (Open Virtual Platforms)+ TLM (Transaction Level Modeling)+systemC to create a virtual platform, achieving a 16 xl6 irregular mesh topology of heterogeneous systems. Finally the routing scheme is applied to test specific real application network instances, and the result shows its connectivity and efficiency.

关键词： network on chip routing algorithms irregular mesh network.

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A Novel Structure of Dynamic Configurable Scan Chain Bypassing Unconcerned Segments on the Fly

A Novel Structure of Dynamic Configurable Scan Chain Bypassi...

引用

International Conference on asic

作者： Shengye Wang Wei Cao Lingli Wang Na Wang Ping Tao State Key Lab of ASIC and System Fudan University Shanghai China East China Institute of Computer Technology Shanghai China

Most of the implementations of boundary scan chains are of fixed length, typically hundreds or thousands. Because the whole chain is scanned every time, many clock cycles are wasted when only a small part of it is concerned. In this paper, a novel structure of configurable boundary scan chain is proposed. Its length and content can be reconfigured without interrupting the chip's functionality. Experimental result shows that the maximum frequency can be as high as 510.4MHz for a full-configurable chain with 512 cells, under 32 nm process, which is 15.7x better than the intuitive method. The proposed structure has been applied to a processor prototype design, and is expected to meet requirements of different applications.

关键词： JTAG Boundary Scan Chain Reconfigurable Segment Tree

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Efficient implementation of OFDM inner receiver on a programmable multi-core processor platform

Efficient implementation of OFDM inner receiver on a program...

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作者： Fan, Wenhua Chen, Chen Chen, Yun Yu, Zhiyi Zeng, Xiaoyang State Key Lab. of ASIC and System Department of Microelectronics Fudan University Shanghai 201203 China

This paper presents an efficient implementation of OFDM inner receiver on a programmable multi-core processor platform with CMMB as an application. The platform consists of an array of programmable SIMD processors interconnected in a 2-D mesh network, which can provide high performance and is quite suitable for wireless communication applications. Implemented on one cluster with 8 cores, the receiver includes symbol timing, carrier frequency offset and sampling frequency offset synchronization, channel estimation and equalization. Multiple optimization techniques are explored to improve system throughput such as: task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access and route-length-minimization task mapping techniques. Besides, efficient memory strategy and specific instructions for complex computation increase the performance. The simulation results show that the inner receiver could achieve a throughput of up to 120 Mbps when operating at 750 MHz. © 2012 The Institute of Electronics, Information and Communication Engineers.

关键词： Orthogonal frequency division multiplexing

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