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检索条件"机构=ASIC and System State-key Lab"

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The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

引用

43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

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Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints 23

Toward Optimal Filler Cell Insertion with Complex Implant La...

引用

Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Peng Zou Guohao Chen Zhifeng Lin Jun Yu Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China

ISBN: (纸本)9798350323481

Modern circuits often contain standard cells of different threshold voltages (multi-VTs) to achieve a better trade-off between timing and power consumption. Due to the heterogeneous cell structures, the multi-VTs cells impose various implant layer constraints, further complicating the already time-consuming filler cell insertion process. In this paper, we present a fast and near-optimal algorithm to solve the filler insertion problem with complex implant layer rules and minimum filler width constraints. We first propose an inference-driven detecting algorithm to identify each design rule violation accurately. Then, a dynamic-programming-based insertion method is developed to reduce the implant layer violations. Finally, we design a contour-driven violation refinement strategy to further improve manufacturability. Experimental results show that our algorithm can reduce the number of violations significantly compared with state-of-the-art works. Besides, with our identifier in the legalization stage, we can avoid conflicts in advance and solve almost all violations after filler insertion in industrial cases.

关键词： filler insertion

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Modeling of CMOS Transistors from 0.18μm Process by Artificial Neural Network

Modeling of CMOS Transistors from 0.18μm Process by Artific...

引用

2021 China Semiconductor Technology International Conference, CSTIC 2021

作者： Wei, JiaHao. Zhao, Tian. Zhang, Zheng. Wan, Jing State Key Lab of Asic and System School of Information Science and Engineering Fudan University Shanghai China

ISBN: (纸本)9781665449458

In this work, we developed a new transistor model that can be used to simulate analog circuits. Our model uses ANN to capture the electrical characteristics of transistors instead of the traditional physics-driven model. By preprocessing the transistor data, high-precision modeling is achieved. N-type and p-type transistors with various widths and lengths are fabricated with the 0.18μm analog process in the foundry. ANN modeling on these transistors shows high precision compared with the BSIM3.3 transistor model provided by the foundry. The results show that the DC characteristics of the ANN model are more accurate than the BSIM3.3 transistor model, and have better capture on the on-resistance of the MOSFET. © 2021 IEEE.

关键词： Transistors

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S-SIFT: A Simple SIFT Algorithm with High Efficiency

S-SIFT: A Simple SIFT Algorithm with High Efficiency

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International Conference on Solid-state and Integrated Circuit Technology

作者： Yixue Wang Yujie Huang Liyuan Peng Mingyu Wang Wenhong Li Minge Jing Xiaoyang Zeng State Key Lab of ASIC & System Fudan University Shanghai China Shanghai ExploreX Technology Co. Ltd. Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

Finding distinctions and connections between multiple visual targets through the detection of keypoints has become one of the research hot-spots in the field of computer vision. SIFT has received wide recognition and attention for its powerful performance in image match. However, the original SIFT has high complexity and time-consuming problems. In this paper, we propose Simple SIFT (S-SIFT), an improved SIFT algorithm in which the construction of Gaussian pyramid and the order of detection steps have been changed. Through the collaborative improvement and optimization on the scale space and algorithm framework, a more efficient local keypoints detecting method is achieved. Experiments demonstrat that SSIFT guarantees satisfactory accuracy with a significant reduction in the computational overhead. Meanwhile, S-SIFT is robust to common image deformations such as rotation, scale change and affine.

关键词： Integrated circuit technology Visualization Computer vision Image recognition Accuracy Deformation Collaboration Complexity theory Optimization

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Conditional Cycle Termination RANSAC

Conditional Cycle Termination RANSAC

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International Conference on Solid-state and Integrated Circuit Technology

作者： Tong Jiang Yujie Huang Liyuan Peng Mingyu Wang Wenhong Li Minge Jing Xiaoyang Zeng State Key Lab of ASIC & System Fudan University Shanghai China Shanghai ExploreX Technology Co. Ltd. Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

In the field of computer vision, the acquired dataset usually contains a certain number of outliers and noise, which leads to errors in the estimated mathematical model. RANSAC estimates model parameters by randomly selecting a subset of the data, reducing the impact of these outliers and noise. However, for datasets with a high proportion of inliers, the traditional RANSAC has to perform a large number of cyclic modeling operations after finding the correct model. In this paper, a conditional termination verification strategy for RANSAC is presented. We boldly terminated the cycle operation early which reduced the amount of computation by 17.78% and increased the computation speed by 34.09%.

关键词： Integrated circuit technology Computer vision Computational modeling Noise Mathematical models Data models Integrated circuit modeling

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A Low-latency Multi-format Carrier Phase Recovery Hardware for Coherent Optical Communication

A Low-latency Multi-format Carrier Phase Recovery Hardware f...

引用

IEEE Asia-Pacific Conference on Circuits and systems

作者： Changlong Lv Liyu Lin Honghui Deng Junhui Wang Yun Chen The State Key Lab of ASIC & System Fudan University Shanghai China

Fast and accurate estimation of carriers is particularly vital in modern coherent optical communication. Achieving a real-time system with low latency and high throughput is challenging. The implementation structure of the real-time system is essential due to the increasing complexity of algorithms and data decimals. This paper proposes a carrier phase recovery (CPR) implementation based on blind phase search (BPS) with data multiplexing. All the computations are performed in cartesian coordinates without using coordinate conversion and standard multiplier or DSP. When evaluating this circuit structure on the Xilinx ZCU102 platform, the clock frequency can reach 620MHz, and the latency of processing 79.3Gbps 16QAM signal is 18 clock cycles.

关键词： Pipelines Parallel processing Throughput Optical fiber communication Real-time systems Hardware Table lookup

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An Approximate-Computing-Based Adaptive Equalizer for Polarization Mode Dispersion

An Approximate-Computing-Based Adaptive Equalizer for Polari...

引用

IEEE Asia-Pacific Conference on Circuits and systems

作者： Liyu Lin Junhui Wang Xiaoyang Zeng Yun Chen State Key Lab of ASIC & System Fudan University Shanghai China

Computational complexity is the most significant defect of coherent optical communication, which consumes a large area and leads to high power consumption, especially for the adaptive filter used for polarization mode dispersion (PMD). In this paper, we implement a 9-tap intro-polarization and 1-tap inter-polarization equalizer, which reduces 34.4% multiplication of the conventional structure. Besides, we proposed an approximate multiplier to save 44.6% full adder. Under the QPSK modulation, the proposed equalizer has a throughput of 114Gb/s and a power of 463mW at 1.786GHz. Synthesis shows that the area of the proposed 16-way parallel adaptive equalizer is 0.365mm2 with a 28 nm process, which has an improvement of 27.86% in area, and 37.88% in energy efficiency to the fix-point structure.

关键词： Optical losses Phase shift keying Power demand Modulation Adaptive equalizers Throughput Optical fiber communication

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Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs

Effective Analytical Placement for Advanced Hybrid-Row-Heigh...

引用

Asia and South Pacific Design Automation Conference

作者： Yuan Wen Benchao Zhu Zhifeng Lin Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China

Recently, hybrid-row-height designs have been introduced to achieve performance and area co-optimization in advanced nodes. Hybrid-row-height designs incur challenging issues to layout due to the heterogeneous cell and row structures. In this paper, we present an effective algorithm to address the hybrid-row-height placement problem in two major stages: (1) global placement, and (2) legalization. Inspired by the multi-channel processing method in convolutional neural networks (CNN), we use the feature extraction technique to equivalently transform the hybrid-row-height global placement problem into two sub-problems that can be solved effectively. We propose a multi-layer nonlinear framework with alignment guidance and a self-adaptive parameter adjustment scheme, which can obtain a high-quality solution to the hybrid-row-height global placement problem. In the legalization stage, we formulate the hybrid-row-height legalization problem into a convex quadratic programming (QP) problem, then apply the robust modulus-based matrix splitting iteration method (RMMSIM) to solve the QP efficiently. After RMMSIM-based global legalization, Tetris-like allocation is used to resolve remaining physical violations. Compared with the state-of-the-art work, experiments on the 2015 ISPD Contest benchmarks show that our algorithm can achieve 7%; shorter final total wirelength and $2.23 \times $ speedup.

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A Low Power Real-Time DC Removal Circuit for PPG Readout 14

A Low Power Real-Time DC Removal Circuit for PPG Readout

引用

14th IEEE International Conference on asic, asicON 2021

作者： Wei, Tingting Wang, Qiong Yuan, Zhu Hong, Zhiliang Fudan University State Key Lab. of ASIC and System Dept. of Microelectronics Shanghai201203 China

ISBN: (纸本)9781665411493

A low-power real-time DC removal circuit for PPG readout is proposed. A moving average filter is used to extract real-time DC voltage. Four sampling capacitors are used, three of which are used for storing the sampled input voltages, and the remaining one is used to store the average value. As the circuit continues to cycle, the weight of the older average voltage is getting lower and lower, to achieve the moving average. The removal operation is implemented by a switched capacitor subtractor with a low-power class AB amplifier. The proposed circuit is embedded between the transimpedance amplifier and the quantizer. A multi-phase clock generator is used to generate switch control signals. Implemented in 0.18μm CMOS technology, simulation results show that this DC removal circuit can remove real-time DC offset and suppress slow DC drift. The simulated SNDR improvement of the proposed circuit is 40.5dB. The power consumption of the proposed circuit is 6 μW under the supply voltage of 1.2V. © 2021 IEEE.

关键词： Power amplifiers

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An Analytical Placement Algorithm with Routing topology Optimization

An Analytical Placement Algorithm with Routing topology Opti...

引用

Asia and South Pacific Design Automation Conference

作者： Min Wei Xingyu Tong Zhijie Cai Peng Zou Zhifeng Lin Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China Center for Discrete Mathematics and Theoretical Computer Science Fuzhou University Fuzhou China

Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer.

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