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China Semiconductor Technology International Conference (CSTIC)

作者： Jiaxin. Zuo Fei. Li Jing. Wan State key lab of ASIC and System School of Information Science and Engineering Fudan University Shanghai China Suzhou Foohu Technology Co. Ltd.

In this work, we explored an efficient automatic layout routing algorithm for connecting the power and ground pins in analog integrated circuits. A rectilinear minimal spanning tree (RMST) algorithm for two sets of pins is developed, in which minimal spanning tree is used to form the initial connections between pins. The obstacle-avoiding maze routing algorithm is used to break and reconnect the power and ground nets to avoid any short circuit. The genetic algorithm (GA) is further introduced to optimize the total connection wirelength. We also expanding the wire width to avoid electromigration and IR-drop.

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Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search

Automated and Agile Design of Layout Hotspot Detector via Ne...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Zihao Chen Fan Yang Li Shang Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China China and Shanghai Key Laboratory of Data Science School of Computer Science Fudan University Shanghai China

This paper presents a neural architecture search scheme for chip layout hotspot detection. In this work, hotspot detectors, in the form of neural networks, are modeled as weighted directed acyclic graphs. A variational autoencoder maps the discrete graph topological space into a continuous embedding space. Bayesian Optimization performs neural architecture search in this embedding space, where an architecture performance predictor is employed to accelerate the search process. Experimental studies on ICCAD 2012 and ICCAD 2019 Contest benchmarks demonstrate that, the proposed scheme significantly improves the agility of previous neural architecture search schemes, and generates hotspot detectors with competitive detection accuracy, false alarm rate, and inference time.

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TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning

TOTAL: Topology Optimization of Operational Amplifier via Re...

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IEEE International Symposium on Quality Electronic Design

作者： Zihao Chen Songlei Meng Fan Yang Li Shang Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai China China and Shanghai Key Laboratory of Data Science School of Computer Science Fudan University Shanghai China

With ever-increasing design complexity and stringent time-to-market pressure, automated topology synthesis tools for operational amplifiers are required to produce designs meeting different specifications. This paper proposes TOTAL, a reinforcement learning-based topology optimization method for operational amplifiers. We decompose the circuit topology design as a Markov decision process to solve the high dimensionality of the design space, with the three-stage cascode paradigm fixed to avoid meaningless structures. Therefore, starting from a basic behavior-level topology, an agent modifies the circuit step by step. Specifically, this agent mainly adopts a graph neural network to understand each design state, including specifications and the design history, and a convolutional neural network to modify the current topology. Every completed circuit is then simulated and evaluated by a customized reward function to guide the agent in finding qualified circuits, among which only the optimal one ever recorded is mapped to the transistor level for further evaluation. Experimental results show that the trained agent can not only generate high-performance circuits, but also be reusable by transferring to other specifications as a pre-trained model and achieving competitive results.

关键词： Operational amplifiers Circuit topology Network topology Optimization methods Reinforcement learning Markov processes Topology

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A High-precision Stochastic Solver for Steady-state Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions

A High-precision Stochastic Solver for Steady-state Thermal ...

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IEEE International Conference on Computer-Aided Design

作者： Longlong Yang Cuiyang Ding Changhao Yan Dian Zhou Xuan Zeng Microelectronics Department State Key Lab of ASIC & System Fudan University China University of Texas at Dallas Dallas USA

In this work, we propose a path integral random walk (PIRW) solver, the first accurate stochastic method for steady-state thermal analysis with mixed boundary conditions, especially involving Fourier heat transfer Robin boundary conditions. We innovatively adopt the strictly correct calculation of the local time and the Feynman-Kac functional eˆ c (t) to handle Neumann and Robin boundary conditions with high precision. Compared with ANSYS, experimental results show that PIRW achieves over 121× speedup and over 83× storage space reduction with a negligible error within 0.8°C at a single point. An application combining PIRW with low-accuracy ANSYS for the temperature calculation at hot-spots is provided as a more accurate and faster solution than only ANSYS used.

关键词： Three-dimensional displays Design automation Scalability Integral equations Boundary conditions Finite element analysis Thermal analysis

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Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement 21

Late Breaking Results: Incremental 3D Global Routing Conside...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Peng Zou Zhifeng Lin Chenyue Ma Jun Yu Jianli Chen State Key Lab of ASIC & System Fudan University Shanghai China College of Mathematics and Computer Science Fuzhou University Fuzhou China State Key Lab of ASIC & System Fudan University Shanghai China and College of Mathematics and Computer Science Fuzhou University Fuzhou China

ISBN: (纸本)9781665432740

Placement and routing are two key problems in VLSI physical design. However, there may be out of sync between the two problems with congestion and routing resources. Therefore, it is desirable to design an efficient and highly coupled placement and routing engine. This paper proposes an incremental 3D global routing engine considering cell movement and complex routing constraints to relocate cells and reroute nets. We develop an efficient movement evaluation method to find desired locations and estimated routing resources for each cell. Then, we adopt an iterative approach to move cells to reduce routing resources. To reduce the time consumption of rerouting, we propose two technologies (searching space reduction and data structure optimization) to speed up the rerouting process. Compared with the participating teams at the 2020 CAD Contest at ICCAD based on the contest benchmarks, experiment results show that our proposed algorithm achieves the best runtime and routing resources while satisfying all the routing constraints.

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RLCkt: An Analog Circuit Automatic Sizing Sage Based on Reinforcement Learning

RLCkt: An Analog Circuit Automatic Sizing Sage Based on Rein...

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China Semiconductor Technology International Conference (CSTIC)

作者： Wangge Zuo Lingge Liu Fei Li Yifei Huang Liqian Zhang Jing Wan School of Information Science and Engineering State key lab of ASIC and System Fudan University Shanghai China Suzhou Foohu Technology Co. Ltd. Shanghai China

Automated solutions for sizing analog circuits have gained significant interest due to the labor-intensive nature of the task in a typical design cycle, especially with technology development and circuit scaling. This study introduces the RLCkt, an Analog Circuit Automatic Sizing Sage, which utilizes reinforcement learning (RL) and the SPICE simulator to automatically adjusts design parameters to meet performance metrics. After several hours of training, RLCkt runs 94 times faster than a traditional generic algorithm with comparable performance. Additionally, its generalization capability surpasses that of state-of-the-art methods.

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Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization 21

Automated Compensation Scheme Design for Operational Amplifi...

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Proceedings of the 58th Annual ACM/IEEE Design Automation Conference

作者： Jialin Lu Liangbo Lei Fan Yang Changhao Yan Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University Shanghai P. R. China

ISBN: (纸本)9781665432740

Operational amplifier is a basic component for analog circuit design. The compensation network of an operational amplifier is crucial to improve the stability of the operational amplifier. In this paper, we present an automated compensation scheme design approach for operational amplifiers. We map the behavioral-level description of the operational amplifier to an acyclic graph and transfer the compensation design problem into a topology optimization problem. A feature mapping method is proposed to encode the graph and a bi-level Bayesian optimization approach is proposed to efficiently solve the topology optimization problem. Experimental results show that our proposed method can obtain competitive three-stage operational amplifiers compared to manual designs.

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Efficient Model-Based OPC via Graph Neural Network

Efficient Model-Based OPC via Graph Neural Network

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Electronics Design Automation (ISEDA), International Symposium of

作者： Shuyuan Sun Xuelian Chen Fan Yang Bei Yu Shang Li Xuan Zeng State Key Lab of ASIC & System School of Microelectronics Fudan University China Cogenda Inc China Department of Computer Science and Engineering The Chinese University of Hong Kong China

As feature size continues to shrink and light source wavelengths remain unchanged, the optical diffraction effects seriously degrade chip yield. Optical proximity correction (OPC) has become an essential step for chip manufacturability. However, OPC cannot achieve satisfactory mask correction results in an affordable number of iterations on some layouts, delaying the chip design cycle. In this paper, we propose to use the Graph Neural Network (GNN) to predict the initial mask correction and speed up model-based OPC. We design a graph model to represent the chip layout, with segments represented as graph nodes and the diffraction effects between them represented as graph edges. The GNN is used to obtain the embedding of the segment, and we predict the shift value based on its output. The proposed GNN-based predictor enhances the original OPC to find a good correction solution for full-chip-size masks in fewer iterations. compared with the original OPC method, experimental results on 55nm and 32nm full chip designs show that the proposed GNN-based OPC method reduces the number of iterations up to 75% and the acquired mask of comparable quality.

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Memristor-based in-situ convolutional strategy for accurate braille recognition

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Science China Materials 2024年第12期67卷 3986-3993页

作者： Xianghong Zhang Congyao Qin Wenhong Peng Ningpu Qin Enping Cheng Jianxin Wu Yuyang Fan Qian Yang Huipeng Chen Institute of Optoelectronic Display National&Local United Engineering Lab of Flat Panel Display TechnologyFuzhou UniversityFuzhou 350002China Zhicheng College Fuzhou UniversityFuzhou 350002China Fujian Science&Technology Innovation Laboratory for Optoelectronic Information of China Fuzhou 350100China State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China

Signal processing has entered the era of big data,and improving processing efficiency becomes *** computing architectures face computational efficiency limitations due to the separation of storage and *** circuits based on multi-conductor devices enable full hardware convolutional neural networks(CNNs),which hold great potential to improve computational ***,when processing large-scale convolutional computations,there is still a significant amount of device redundancy,resulting in low computational power consumption and high computational ***,we innovatively propose a memristor-based in-situ convolutional strategy,which uses the dynamic changes in the conductive wire,doping area,and polarization area of memristors as the process of convolutional operations,and uses the time required for conductance switching of a single device as the computation result,embodying convolutional computation through the unique spiked digital signal of the *** strategy reasonably encodes complex analog signals into simple digital signals through a memristor,completing the convolutional computation at the device level,which is essential for complex signal processing and computational efficiency *** on the implementation of device-level convolutional computing,we have achieved feature recognition and noise filtering for braille *** believe that our successful implementation of convolutional computing at the device level will promote the construction of complex CNNs with large-scale convolutional computing capabilities,bringing innovation and development to the field of neuromorphic computing.

关键词： convolutional computing multi-conductor memristor conductive filaments

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A Robust Global Routing Engine with High-accuracy Cell Movement under Advanced Constraints

A Robust Global Routing Engine with High-accuracy Cell Movem...

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IEEE International Conference on Computer-Aided Design

作者： Ziran Zhu Fuheng Shen Yangjie Mei Zhipeng Huang Jianli Chen Jun Yang National ASIC System Engineering Center Southeast University Nanjing China Department of Mathematics and Theories Peng Cheng Laboratory Shenzhen China State Key Lab of ASIC & System Fudan University Shanghai China

Placement and routing are typically defined as two separate problems to reduce the design complexity. However, such a divide-and-conquer approach inevitably incurs the degradation of solution quality due to the correlation/objectives of placement and routing are not entirely consistent. Besides, with various constraints (e.g., timing, R/C characteristic, voltage area, etc.) imposed by advanced circuit designs, bridging the gap between placement and routing while satisfying the advanced constraints has become more challenging. In this paper, we develop a robust global routing engine with high-accuracy cell movement under advanced constraints to narrow the gap and improve the routing solution. We first present a routing refinement technique to obtain the convergent routing result based on fixed placement, which provides more accurate information for subsequent cell movement. To achieve fast and high-accuracy position prediction for cell movement, we construct a lookup table (LUT) considering complex constraints/objectives (e.g., routing direction and layer-based power consumption), and generate a timing-driven gain map for each cell based on the LUT. Finally, based on the prediction, we propose an alternating cell movement and cluster movement scheme followed by partial rip-up and reroute to optimize the routing solution. Experimental results on the ICCAD 2020 contest benchmarks show that our algorithm achieves the best total scores among all published works. Compared with the champion of the ICCAD 2021 contest, experimental results on the ICCAD 2021 contest benchmarks show that our algorithm achieves better solution quality in shorter runtime.

关键词： Power demand Runtime Design automation Voltage Benchmark testing Routing Prediction algorithms

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