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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Kuang, Huizhen Zheng, Su Wang, Lingli Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Due to high energy efficiency, runtime reconfigurability, and low hardware cost, coarse-grained reconfigurable architecture (CGRA) is promising in many rapid-evolving applications. Nevertheless, CGRA architecture design is an extremely costly task that requires searching a vast design space. We propose a fast automated design space exploration (DSE) algorithm based on Bayesian optimization (BO) to search the design space modeled by a black-box. Experimental results show that our approach significantly outperforms simulated annealing (SA) and genetic algorithm (GA). The optimized architecture has dramatic mapping performance improvements while saving the hardware area by 36% and 12% respectively compared with the optimized architectures by GA and SA. © 2022 IEEE.

关键词： Simulated annealing

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A Compact I/Q Network with Center-Tap Coupled Transformer-Based Quadrature Hybrids for Millimeter-Wave Applications 9

A Compact I/Q Network with Center-Tap Coupled Transformer-Ba...

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9th IEEE MTT-S International Wireless Symposium, IWS 2022

作者： Zeng, Chao Luo, Wei Xu, Hongtao Fudan University State Key Laboratory of Asic and System China ICLegend Micro Shanghai China

ISBN: (数字)9781665481977

ISBN: (纸本)9781665481977

In this paper, a compact broadband in-phase/quadrature (I/Q) network is realized based on transformer-based quadrature hybrids. The coupling capacitors of the proposed hybrid locate at the center taps of the transformer. All output ports of the center-tap coupled quadrature hybrid locate at the same side of the transformer, which makes signal path and power routing much easier. Based on the center-tap coupled hybrid, the proposed I/Q network shows a good performance with less area. A lumped-element model of the center-tap coupled quadrature hybrid is also investigated. Based on the 40-nm CMOS process, an I/Q network with 2-stage transformer-based quadrature hybrids is implemented. Simulation results demonstrate that the proposed structure achieves an image rejection ratio (IRR) of more than 35 dB from 17 GHz to 31 GHz. Furthermore, the area of the proposed structure is 392*379 um2. © 2022 IEEE.

关键词： Millimeter waves

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Fully sprayed MXene-based high-performance flexible piezoresistive sensor for image recognition

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Nano Materials Science 2024年第1期6卷 77-85页

作者： Zhi-Dong Zhang Xue-Feng Zhao Qing-Chao Zhang Jie Liang Hui-Nan Zhang Tian-Sheng Zhang Chen-Yang Xue Key Laboratory of Instrumentation Science&Dynamic Measurement of Ministry of Education North University of ChinaTaiyuan030051People's Republic of China State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan UniversityShanghai200433People's Republic of China Shanxi Hosipital of Acupuncture and Moxibustion Taiyuan030006People's Republic of China

High-performance flexible pressure sensors provide comprehensive tactile perception and are applied in human activity monitoring,soft robotics,medical treatment,and human-computer ***,these flexible pressure sensors require extensive nano-architectural design and complicated manufacturing and are ***,a highly sensitive,flexible piezoresistive tactile sensor is designed and fabricated,consisting of three main parts:the randomly distributed microstructure on T-ZnOw/PDMS film as a top substrate,multilayer Ti_(3)C_(2)-MXene film as an intermediate conductive filler,and the few-layer Ti_(3)C_(2)-MXene nanosheetbased interdigital electrodes as the bottom *** MXene-based piezoresistive sensor with randomly distributed microstructure exhibits a high sensitivity over a broad pressure range(less than 10 kPa for 175 kPa^(-1))and possesses an out-standing permanence of up to 5000 ***,a 16-pixel sensor array is designed,and its potential applications in visualizing pressure distribution and an example of tactile feedback are *** fully sprayed MXene-based pressure sensor,with high sensitivity and excellent durability,can be widely used in,electronic skin,intelligent robots,and many other emerging technologies.

关键词： Piezoresistive sensor Ti_(3)C_(2)-MXene T-ZnOw/PDMS film Randomly distributed microstructure

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An Adaptive Threshold Analog Front-End Circuit for Direct ToF LiDAR

An Adaptive Threshold Analog Front-End Circuit for Direct To...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Jianping Guo Xiaoyang Zeng Wenhong Li Mingyu Wang State-key Laboratory of ASIC and system Fudan University Shanghai CHINA

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

The analog front-end (AFE) circuit of the light detection and ranging (LiDAR) receivers need to provide time-of-flight (ToF) when the laser echo arrives. Accurate ToF is crucial for the ranging accuracy of LiDAR receivers. However, targets with different reflectivity will give different timing results even at the same distance due to the light intensity. This paper proposes an AFE circuit for LiDAR receiver. This AFE circuit can adaptively adjust the threshold based on photocurrent to reduce walk error under different light intensities. Proposed AFE is implemented in 55nm CMOS process. Simulation results show that within the photocurrent range of 3 to 20 uA, the timing error is less than 0.8 ns.

关键词： Resistors Reflectivity Laser radar Accuracy Sensitivity Simulation Receivers Distance measurement Timing Photoconductivity

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Multi-Sampling Mode CDAC Design for a 12-Bit 200MS/s Pipelined-SAR ADC

Multi-Sampling Mode CDAC Design for a 12-Bit 200MS/s Pipelin...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Tianyu Zhang Fan Ye Shunli Ma State-key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

This paper proposes a multi-sampling mode capacitor DAC (CDAC) for a 12-bit 200MS/s pipelined-SAR ADC, addressing the issue of overfitting in neural network-based calibrations. By implementing normal, offset, and proportional sampling modes, the design ensures the linearity of the ADC's transfer function. The proposed CDAC utilizes a bottom-plate sampling method and a high-linearity bootstrap circuit. Simulation results demonstrate that the proposed ADC achieves an SFDR of around 75dB and an ENOB of approximately 10.8bits across all sampling modes, validating the effectiveness of the design in enhancing ADC performance.

关键词： Integrated circuit technology Simulation Capacitors Transfer functions Linearity Logic gates Sampling methods Approximation algorithms Calibration Overfitting

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Integration of Droplet Transport and Mixing on EWOD 16

Integration of Droplet Transport and Mixing on EWOD

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Gao, Shang Rui, Xichuan Zhou, Jia Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Microdroplet transportation and mixing are indispensable functions in lab-on-chip applications. Additional components to conventional microfluidic platforms have solved the problem but with the big increase in the complexity of system integration. Here we propose an EWOD (Electrowetting on Dielectrics) design of driving electrode with a micro-barrier structure that enables the droplet mixing simultaneously along with the unidirectional transportation controlled by only two signals. The nesting asymmetrical electrodes not only provide the unidirectional driving pressure to the droplets, but also enhance the mixing of droplets by the specific micro-barrier structure through the curvilinear and fluctuating movement of the droplets. This design demonstrates a new approach to functional integration of EWOD microfluidic chips, which is of great significance in bioanalysis, especially in POCT (Point of Care Technology). © 2022 IEEE.

关键词： Drops

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DNNMapper: An Elastic Framework for Mapping DNNs to Multi-die FPGAs

DNNMapper: An Elastic Framework for Mapping DNNs to Multi-di...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Shuyang Li Xilang Zhou Haodong Lu Kun Wang State Key Laboratory of ASIC & System Fudan University Shanghai China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Deep Neural Networks (DNNs) have stimulated intensive FPGA-based acceleration solutions, and multi-die FPGAs offer abundant resources for implementing large-scale DNN workloads. However, current FPGA frameworks overlook the opportunities of optimization on multi-die FPGAs. In this paper, we propose an automated framework named DNNMapper, for mapping DNNs to multi-die FPGAs. With careful consideration of the unique architectural characteristics and resource constraints of multi-die FPGAs, DNNMapper involves model partitioning and resource allocation as two critical processes that map DNN layers onto respective FPGA dies and efficiently allocate hardware resources. DNNMapper employs a co-design engine based on a genetic algorithm, which co-optimizes model partitioning and resource allocation. Experimental results demonstrate that accelerators generated by DNNMapper offer superior performance and scalability, achieving up to 2× higher throughput and 1.3× to 1.9× higher DSP density. Moreover, our accelerator demonstrates a frequency improvement from 1.28× to 1.69×.

关键词： Scalability Artificial neural networks Throughput Hardware Resource management Integrated circuit modeling Field programmable gate arrays

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OrderMap: A CGRA Mapping Algorithm based on DFG Analysis and Graph Homomorphism 16

OrderMap: A CGRA Mapping Algorithm based on DFG Analysis and...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Li, Jiangnan Zheng, Su Wang, Lingli Yin, Wenbo Fudan University State Key Laboratory of Asic and System Department of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Coarse-grained reconfigurable architecture (CGRA) accelerator is a promising solution in fields such as deep learning and edge computing. One of the difficult problems to design the accelerator is to map the data flow graph (DFG) to the architecture efficiently. The previous mapping algorithms based on graph structure mainly focus on optimization during the placement and routing stage, which may fall into a local minimum and lead to an increase in initiation interval (II). We propose a CGRA mapping algorithm, OrderMap, based on DFG analysis and graph homomorphism. It analyzes the DFG structure information to decide the node mapping order, followed by placement, and routing. Experimental results show that our algorithm is faster than CGRA-ME with smaller IIs. Compared with FastCGRA based on the depth-first order, OrderMap is 22.3 × faster with the same mapping results. © 2022 IEEE.

关键词： Deep learning

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Addressing and two-dimensional driving of droplets on single-sided continuous optoelectrowetting chip 16

Addressing and two-dimensional driving of droplets on single...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Enqing Wang, Cui Riaud, Antoine Zhou, Jia Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Digital microfluidics(DMF) represented by electrowetting on dielectrics(EWOD) has a broad application prospect in bioassay, chemical synthesis and drug discovery, but currently EWOD technology faces problems such as wiring bottleneck and complexity of droplet detection circuits. Optoelectrowetting(OEW) addresses the wiring bottleneck issue by using light pattern to control droplets. To date, light patterns have been designed by hand and have only allowed one dimensional manipulation. In this paper, we introduced a method using programmable optical patterns to modulate the electric field distribution on the chip, which realized two dimensional manipulation of droplet on the chip. At the same time, machine learning target detection algorithms YOLOv3 was used to accurately detection of droplets the self-addressing of light patterns. © 2022 IEEE.

关键词： Digital microfluidics

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A 12-Bit 250-MS/s Voltage-Time Domain Hybrid ADC 16

A 12-Bit 250-MS/s Voltage-Time Domain Hybrid ADC

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhao, Yutong Ye, Fan Ren, Junyan Fudan University State Key Laboratory of Asic and System Department of Microelectronics Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This article presents a 12-bit 250-MS/s voltage-time domain hybrid analog-to-digital converter (ADC). In the proposed ADC, the first stage is a binary-weighted SAR ADC, and the second stage is a coarse-fine time-to-digital converter (TDC), connected with a highly linear dynamic voltage-to-time converter (VTC). Using the combination of voltage and time domain quantization, this hybrid architecture is power efficient and can benefit from technology scaling. The time domain folding of the ring oscillator leads to an inherently linear operation. The prototype ADC is simulated in TSMC 28nm CMOS process with a 0.9V power supply, achieving a 55.62-dB SNDR and a 67.16-dB SFDR at Nyquist input. The power consumption is 1.36 mW, obtaining a Walden figure of merit (FoM) of 11.07 fJ/conv.- step. © 2022 IEEE.

关键词： Frequency converters

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