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A 26-39.5 GHz Two-Path Voltage-Combined Power Amplifier with Bandwidth Broadening Technique in 22nm FD-SOI 16

A 26-39.5 GHz Two-Path Voltage-Combined Power Amplifier with...

引用

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Cao, Xun Wu, Tianxiang Ma, Shunli Fudan University State Key Laboratory of Asic & System Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper presents the analysis and design of a 26-39.5GHz power amplifier. In order to achieve high output power, we adopt the two-path voltage-combined topology. A voltage-mode power combiner is designed using strongly-coupled transformers for low insertion loss. The cascode structure is applied in the power-stage for high power gain and output power. The MOS-capacitor based neutralization technique and gate-shorted common gate transistors are applied to boost power gain and enhance stability. Meanwhile, for expanding the operation bandwidth of the power amplifier, weakly-coupled transformer matching technique is applied in the interstage and input matching network. The overall circuit is based on 22-nm FD-SOI process. Simulation results show that the power amplifier has a 3-dB bandwidth of 13.5GHz, ranging from 26 to 39.5 GHz. At the center frequency of 32.5 GHz, the PA has a power gain of 29 dB. The saturated output power of the power amplifier is 25.1 dBm, and the peak power added efficiency PAE is about 41.2%. The output 1dB compression point is 19.1 dBm. © 2022 IEEE.

关键词： Power amplifiers

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A high-performance RISC-V co-processor architecture for fast IP processing 16

A high-performance RISC-V co-processor architecture for fast...

引用

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Kong, Xinjie He, Weiliang Han, Jun Fudan University State Key Laboratory of Asic and System Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Longest Prefix Matching (LPM) plays an important role in fast IP processing. In this paper, a hardware coprocessor architecture connected to high-performance RISC-V processor is proposed to achieve faster LPM search. By applying specific customized instructions to achieve HW/SW co-processing, we can gain 111% performance improvement for every search iteration. The implementation results under TSMC 28nm technology show that the proposed co-processor can work at 1GHz and only require 0.1% extra area cost (5056 um2 ) compared to the whole system of the Xuantie processor. © 2022 IEEE.

关键词： Coprocessor

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A Dual-Mode ReRAM CIM Macro for Low Power Memory-Augmented Neural Networks 16

A Dual-Mode ReRAM CIM Macro for Low Power Memory-Augmented N...

引用

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Chen, Deyang Guo, Zhiwang Fang, Jinbei Xue, Xiaoyong Fudan University State Key Laboratory of Asic and System Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Learning from a few unseen samples to generalize the feature of new classes is a key challenge for real-time machine intelligence. To resolve this issue, the memory-augmented neural network (MANN) is proposed with an external memory to make use of the learned knowledge patterns to adapt to the new data [1]. A ReRAM computing-in-memory (CIM) macro based on voltage division is proposed to support the MANN operations in this paper. With the same bit-cell but different encoding schemes, the proposed macro is able to realize two different computing paradigms. The proposed complementary structure of bit-cell shows a high energy efficiency in the compute phase. And the simulation result shows that the proposed bit-cell has a good tolerance of device variations as well. © 2022 IEEE.

关键词： RRAM

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Research on Target Detection Algorithm For 77GHz Automotive Radar 16

Research on Target Detection Algorithm For 77GHz Automotive ...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Wu, Jia-Xi Xu, Nuo Wang, Bin Ren, Jun-Yan Ma, Shun-Li Fudan University State-key Laboratory of Asic and System Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Advanced Driver Assistance systems (ADAS) has changed our lives in the field of automobile driving. Radar based automotive systems play an important role in increasing comfort and safety. This paper presents a stimulation of 77GHz frequency-modulated continuous-waveform (FMCW) automotive radar system, which can be used for target detection and objects separation. The system using multiple-input/multiple-output (MIMO) array can measure range, velocity, azimuth and elevation of multiple targets with high angle resolution. Angular separation performance comparisons of 8, 32 and 128 channel MIMO radar sensors are made for real driving scenario. © 2022 IEEE.

关键词： Digital signal processing

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Analytical Modelling of a Hybrid Reluctance Motor Based on Magnetic Equivalent Circuit

Analytical Modelling of a Hybrid Reluctance Motor Based on M...

引用

2023 IEEE International Conference on Industrial Technology, ICIT 2023

作者： Su, Xinyi Yang, Xiaofeng Xu, Yunlang Academy for Engineering and Technology Fudan University Shanghai China Fudan University State Key Laboratory of Asic and System Shanghai China

ISBN: (纸本)9798350336504

This study focuses on the analytical modelling of a hybrid reluctance motor (HRM). For the first time, the nonlinear factors of magnetic leakage, fringing flux, and magnetic saturation in the HRM are all considered in the model. Firstly, the magnetic equivalent circuits (MECs) of the magnet and coils are constructed, where the magnetic leakage and fringing flux are handled by the flux tube method. Secondly, the flux ratio criterion (FRC) is introduced to equate the nonlinear relationship between the magnetic field intensity and magnetic flux density to the relative permeability varying with the magnetic flux density. And the flux of each reluctance is calculated by an iterative algorithm. Then, the resultant force of the mover can be further obtained, and the model of the HRM is completed. Finally, the results of the presented model are compared with those of the existing model and finite element analysis (FEA). It can be concluded that the proposed model significantly improves the modelling accuracy, and can well describe the nonlinear characteristics of the HRM. © 2023 IEEE.

关键词： Reluctance motors

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An OSAA-CFAR Algorithm for 77GHz Millimeter-wave Radar 16

An OSAA-CFAR Algorithm for 77GHz Millimeter-wave Radar

引用

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Xu, Nuo Wu, Jiaxi Wang, Bin Ren, Junyan Ma, Shunli Fudan University State Key Laboratory of Asic and System Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Constant False Alarm Rate (CFAR) is one of the key technologies for radar target detection, which can maintain a certain probability of false alarm during target detection. However, traditional CFAR algorithms only perform better in a certain detection environment and have some drawbacks in other detection environments. This paper proposes an OSAA-CFAR algorithm, which performs the mean calculation and ranking calculation of reference cells, and it has a high detection probability in a uniform clutter environment. It also has good performance in detecting multiple adjacent targets. Finally, the OSAA-CFAR algorithm is verified on 77 GHz millimeter-wave radar and the FPGA-based OSAACFAR hardware implementation is designed using pipelined architecture and its clock frequency can reach up to 300MHz in Xilinx Zynq-7000 FPGA. © 2022 IEEE.

关键词： Millimeter waves

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Design of a 50MHz Bandwidth TIA Using Negative Capacitance 16

Design of a 50MHz Bandwidth TIA Using Negative Capacitance

引用

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Tao, Cong Lei, Liangbo Hong, Zhiliang Huang, Yumei Fudan University State Key Laboratory of Asic and System Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

The transimpedance amplifier (TIA) is a key component in the analog baseband (BB) of a current-mode receiver (RX). It requires low input impedance (Zin) and high linearity up to very high frequencies. However, due to the narrow bandwidth (BW) of the Miller-compensated transconductance amplifier (OTA), Zin often peaks at medium frequency (MF), degrading out-of-band (OOB) linearity. This article aims to remove the peak. To this end, an OTA with 44.8dB open-loop gain and 1.8GHz unity-gain loop bandwidth (UGLB) is proposed. It's based on a two-stage pseudo-differential OTA. Instead of the Miller compensation, which pushes the dominant pole to lower frequency, this paper uses negative capacitance (NC) to push the non-dominant pole to higher frequency, thereby increasing UGLB and phase margin (PM). The TIA, designed and simulated in the TSMC 40nmLP technology, achieves 50MHz BW for 5G sub6GHz wideband RX. Its in-band (IB) and OOB IIP3s are 35.4dBm and 45.2dBm, respectively. Zin is less than 11.4Ω at all frequencies, while consuming 9.4mW from a 1.2V supply. © 2022 IEEE.

关键词： Operational amplifiers

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A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS

A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type T...

引用

作者： Zhang, Jincheng Wang, Yujia Chen, Yong Ren, Junyan Ma, Shunli Fudan University State Key Laboratory of Asic and System Shanghai200433 China University of Macau State-Key Laboratory of Analog and Mixed-Signal Vlsi and IME/ECE-FST China

This article presents a high-power wideband power amplifier (PA) with a four-way power-combining technique for $D$ -band high-resolution radar. The power combiner is based on a two-section Chebyshev impedance converter to achieve a large bandwidth (BW) and is realized with slow wave coplanar waveguides (S-CPWs) to reduce the insertion loss and chip area. Therefore, our developed technique can provide broadband and low-loss power-combining scheme in a very compact size. A high-power PA with four-way combining has been fabricated in a 28-nm CMOS bulk technology. The unit PA uses low- $k$ transformer-based coupled-resonator networks to realize wideband matching. The measured results of the PA prototype demonstrate the peak gain of 22.6 dB, the saturated output power of 16.2 dBm, and the peak power added efficiency of 8.6% at 135 GHz with a 3-dB BW of 28 GHz from 124 to 152 GHz. Meanwhile, the total area of this PA die is merely 0.66 $\times $ 0.73 mm. © 1963-2012 IEEE.

关键词： Power amplifiers

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An AOT Buck Converter with Adaptive TONExtender Achieving 2.5μs Settling Time in 4A Load Transient

An AOT Buck Converter with Adaptive TONExtender Achieving 2....

引用

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022

作者： Zhang, Zhuang Shi, Hanyu Lu, Danzhu Cao, Peng Hong, Zhiliang Fudan University State Key Laboratory of Asic and System Shanghai200433 China

ISBN: (数字)9781665492690

ISBN: (纸本)9781665492690

An adaptive on-time (AOT) buck converter with constant switching frequency and fast transient response is presented. A frequency-locked loop (FLL) is used to achieve constant switching frequency. The on-time (TON) is adjusted by a TON extender to achieve fast transient response. The proposed AOT buck converter is implemented in 0.18μm CMOS process. The simulation results show that the switching frequency is fixed at IMHz under various load condition and the output voltage undershoot and settling time are only 50m V and 2.5μs, respectively during 4A load transient. © 2022 IEEE.

关键词： Buck converter

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Data Flow Graph Partitioning Method for CGRA Temporal Mapping Based on Bayesian Optimization

Data Flow Graph Partitioning Method for CGRA Temporal Mappin...

引用

China Semiconductor Technology International Conference (CSTIC)

作者： Yihan Hu Jiangnan Li Wenbo Yin Lingli Wang Wai-Shing Luk State Key Laboratory of ASIC & System Shanghai China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

Coarse-Grained Reconfigurable Arrays (CGRAs) are attracting more and more attention for their high flexibility and energy efficiency. Due to the limited resources, mapping large data flow graphs (DFGs) that represent application kernels onto a CGRA is difficult, for which partitioning is employed. However, existing partitioning methods in the CGRA domain are unable to solve large kernels. In this work, we propose BOPart, an efficient DFG partitioning method based on Bayesian optimization. This enables the mapping of large DFGs that surpass the capacity of the target CGRA. Moreover, we design a graph coarsening method to reduce the complexity of the partitioning problem, which further improves the performance and convergence of BOPart. BOPart can handle benchmarks with up to 333 operations, surpassing the capability of state-of-the-art temporal mapping and partitioning method, which can only handle benchmarks with up to 94 operations.

关键词： Integrated circuits Benchmark testing Energy efficiency Bayes methods Complexity theory Flow graphs Arrays

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