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检索条件"机构=ASML Technology Development Center"
22 条 记 录,以下是1-10 订阅
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Litho scenario solutions for FinFET SRAM 22nm node
Litho scenario solutions for FinFET SRAM 22nm node
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2009 Lithography Asia Conference
作者: Tseng, Shih-En Wu, Shun-Der Wang, Jacques Kou, Jay Mouraille, Orion Jungblut, Reiner Chiou, Tsann-Bim Finders, Jo Chen, Alek Dusa, Mircea Hsu, Stephen Technology Development Center ASML Taiwan ASML Center of Excellence D and E ASML Taiwan ASML Netherlands Technology Development Center ASML Belgium ASML Brion Technologies United States
For the development of the most cost effective lithographic solutions for the 22nm node, the lithographic process and relevant requirements on CDU and overlay need to be identified. In this work, 22nm logic SRAM is se... 详细信息
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Computational evaluation of critical logic metal layers of pitch 20-24nm and aberration sensitivity in high NA EUV single patterning  2
Computational evaluation of critical logic metal layers of p...
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DTCO and Computational Patterning II 2023
作者: Gao, Weimin Chen, Chun-Kuang Zimmermann, Joerg ASML Technology Development Center Carl Zeiss SMT GmbH
As chip manufacturers seek to reduce the pitch of metal layers, there is growing interest in replacing the multiple patterning process of 0.33NA EUV with a single patterning of high NA (0.55NA) EUV. However, to resolv... 详细信息
来源: 评论
Using cluster analysis to improve the design of component interfaces  08
Using cluster analysis to improve the design of component in...
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ASE 2008 - 23rd IEEE/ACM International Conference on Automated Software Engineering
作者: Adnan, Rahmat Graaf, Bas Van Deursen, Arie Zonneveld, Joost Delft University of Technology Netherlands ASML Netherlands Microsoft Development Center Copenhagen
For large software systems, interface structure has an important impact on their maintainability and build performance. For example, for complex systems written in C, recompilation due to a change in one central heade... 详细信息
来源: 评论
Ultra-fast aerial image simulation algorithm using wavelength scaling and fast Fourier transformation to speed up calculation by more than three orders of magnitude
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Journal of Micro/Nanopatterning, Materials and Metrology 2023年 第2期22卷
作者: Gau, Tsai-Sheng Chen, Po-Hsiung Lin, Burn J. Ko, Fu-Hsiang Chen, Chun-Kung Yen, Anthony National Tsinghua University College of Semiconductor Research Hsinchu Taiwan National Yang Ming Chiao Tung University Department of Material Science and Engineering Hsinchu Taiwan ASML Technology Development Center Hsinchu Taiwan ASML Technology Development Center San JoseCA United States
An ultra-fast image simulation algorithm is proposed. The new algorithm uses full fast-Fourier-transform (FFT) to calculate the aerial image intensity. The wavelength, 193 nm, was scaled to a number of powers of 2, th... 详细信息
来源: 评论
Using intra-field high order correction to achieve overlay requirement beyond sub-40nm node
Using intra-field high order correction to achieve overlay r...
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Metrology, Inspection, and Process Control for Microlithography XXIII
作者: Huang, Chun Yen Chue, I Fu Liu, An-Hsiung Wu, Wen Bin Shin, Chiang Lin Chiou, Tsann-Bim Lee, Juno Chen, Owen Chen, Alek Nanya Technologies Corp. Taoyuan 333 Taiwan Taiwan ASML Technology Development Center Taiwan Taiwan
Overlay requirements for semiconductor devices are getting more demanding as the design rule shrinks. According to ITRS expectation[1], on product overlay budget is less than 8nm for the DRAM 40nm technology node. In ... 详细信息
来源: 评论
EUV lithography introduction at Chipmakers
EUV lithography introduction at Chipmakers
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2011 International Symposium on VLSI technology, Systems and Applications, VLSI-TSA 2011
作者: Wagner, Christian Bacelar, Jose Harned, Noreen Loopstra, Erik Hendriks, Stef De Jong, Ivo Kuerz, Peter Levasier, Leon Van De Kerkhof, Mark Lowisch, Martin Meiling, Hans Ockwell, David Peeters, Rudy Van Setten, Eelco Stoeldraijer, Judon Young, Stuart Zimmerman, John Kool, Ron Chen, Alek ASML Netherlands B.V. De Run 6501 5504 DR Veldhoven Netherlands Carl Zeiss SMT AG 73446 Oberkochen Germany ASML Technology Development Center Asia ASML Taiwan Ltd Hwa-ya Technology Park GueiShan Township Taoyuan County Taiwan
With the 1st NXE:3100, 0.25NA and 0.8 conventional illumination, being operational at a Semiconductor Manufacturer, we enter the next phase in EUVL implementation. Since 2006 process and early device verification has ... 详细信息
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Diffraction-Based Alignment Sensor and Mark Design Optimization to Enable Fine Overlay Accuracy for 50um-Thick Si Wafer Bonded to Glass Wafer in Die-to-Wafer Bonding Applications  26
Diffraction-Based Alignment Sensor and Mark Design Optimizat...
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26th Electronics Packaging technology Conference, EPTC 2024
作者: Tamaddon, Amir-Hossein Jadli, Imene Suhard, Samuel Jourdain, Anne Hsu, Alex Schaap, Charles De Poortere, Etienne Miller, Andy Kennes, Koen Ceulemans, Karl Blanco, Victor imec Kapeldreef 75 Leuven3001 Belgium ASML Technology Development Center Kapeldreef 75 Leuven3001 Belgium ASML Netherlands BV. De Run 6501 Veldhoven5504 DR Netherlands
In this paper, a collective die-to-wafer bonding integration scheme will be investigated. Minimizing the difference between backside and frontside fingerprints using the asml scanner is the primary goal of this study.... 详细信息
来源: 评论
Challenges for Lithography Scaling to 32nm and Below
Challenges for Lithography Scaling to 32nm and Below
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International Symposium on VLSI technology, Systems and Applications
作者: William H Arnold ASML Technology Development Center Tempe AZ USA
Microlithography continues to enable device scaling and manufacturing of high speed microprocessors, high density flash and DRAM memories, as well as SoCs and ASSPs. However, the shrink roadmaps of each device technol... 详细信息
来源: 评论
Diffraction-Based Alignment Sensor and Mark Design Optimization to Enable Fine Overlay Accuracy for 50um-Thick Si Wafer Bonded to Glass Wafer in Die-to-Wafer Bonding Applications
Diffraction-Based Alignment Sensor and Mark Design Optimizat...
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Electronics Packaging technology Conference (EPTC)
作者: Amir-Hossein Tamaddon Imene Jadli Samuel Suhard Anne Jourdain Alex Hsu Charles Schaap Etienne De Poortere Andy Miller Koen Kennes Karl Ceulemans Victor Blanco imec Leuven Belgium ASML Technology Development Center Leuven Belgium ASML Veldhoven DR The Netherlands
In this paper, a collective die-to-wafer bonding integration scheme will be investigated. Minimizing the difference between backside and frontside fingerprints using the asml scanner is the primary goal of this study.... 详细信息
来源: 评论
Experimental Evaluation of Reset Control for Improved Stage Performance
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IFAC-PapersOnLine 2016年 第13期49卷 93-98页
作者: Heertjes, M.F. Gruntjens, K.G.J. van Loon, S.J.L.M. van de Wouw, N. Heemels, W.P.M.H. ASML Mechatronic Systems Development Eindhoven University of Technology Mechanical Engineering Veldhoven Eindhoven Netherlands Eindhoven University of Technology Mechanical Engineering Eindhoven Netherlands Océ Technologies Mechanical Department Venlo Netherlands Department of Civil Environmental and Geo-Engineering University of Minnesota MinneapolisMN55455 United States Delft Center for Systems and Control Delft University of Technology Delft Netherlands
A reset integral controller is discussed that induces improved low-frequency disturbance rejection properties under double integrator control without giving the unwanted increase of overshoot otherwise resulting from ... 详细信息
来源: 评论