The article researches the problem of self-timed (ST) binary counter implementation. ST circuits demonstrate correct operation over a much wider range of supply voltage and ambient temperature, in contrast to synchron...
The article researches the problem of self-timed (ST) binary counter implementation. ST circuits demonstrate correct operation over a much wider range of supply voltage and ambient temperature, in contrast to synchronous counterparts. The reason for this is hardware redundancy, two-phase operating discipline and mandatory acknowledging of the switch completion of all circuit cells in each phase of circuit operation. As a result, ST circuits operate stably no matter the cell delays. Due to their simpler indication, serial ST counters have less hardware redundancy than combinational ST circuits. However, they require the specific procedure organization to implement ST preset. The article examines the circuitry basis for the ST counter implementation and proposes a schematic preset realization ensuring its self-timing and optimal hardware complexity.
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Self-timed (ST) digital circuits, which constitute a subclass of asynchronous circuits, have a number of advantages over synchronous and asynchronous counterparts. Due to the two-phase discipline, redundant data encod...
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ISBN:
(数字)9798331512194
ISBN:
(纸本)9798331512200
Self-timed (ST) digital circuits, which constitute a subclass of asynchronous circuits, have a number of advantages over synchronous and asynchronous counterparts. Due to the two-phase discipline, redundant data encoding and mandatory acknowledging of successful switching completion in each operation phase, ST circuits operate in a wider range of supply voltage and temperature and are more resistant to soft errors. Excessive hardware costs inherent in ST circuits do not play a significant role at the current semiconductor technology development level. However, the lack of qualified developers and automated design tools for ST circuits hamper the wide ST circuits' practical use. The paper considers an approach to the ST circuit design based on the formalized transformation of the original synchronous Verilog-description of a digital circuit into a description of an ST circuit that has all the ST circuit's properties and ensures the ST circuit synthesis with minimal hardware complexity. The most difficult stage of converting a synchronous circuit description into its ST description is sequential unit implementation. It requires taking into account the nuances of the functioning of ST triggers and units based on them. The paper proposes a formalized method for substituting ready-made parameterized templates of typical sequential ST units instead of synchronous counterparts based on extracting the synchronous counterpart's properties and selecting the most suitable ST template.
This paper has emanated from joint research conducted with the financial support of the National Key Research and Development Program of China under Grant No. 2017YFE0135700 and the Bulgarian National science Fund (BN...
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Self-timed (ST) circuits have a number of advantages over synchronous counterparts. They utilize natural interaction between digital units based on data availability. Combinational ST circuits use redundant coding of ...
Self-timed (ST) circuits have a number of advantages over synchronous counterparts. They utilize natural interaction between digital units based on data availability. Combinational ST circuits use redundant coding of information and a two-phase operating discipline, which makes it possible to detect the successful circuit switching completion in each phase. The combinational ST circuit synthesis has been well studied, formalized, and implemented in several existing computer-aided design systems for asynchronous digital units. It is based on dualizing the logical function system in order to convert single information signals into dual-rail signals with a null or unit spacer and supplementing an additional indication subcircuit that detects the completion of ST circuit switching into the current phase. The synthesis of ST circuits with memory is less amenable to formalization. The paper considers the problem of implementing typical ST units with memory, namely latches and flip-flops. It analyzes ST latch and flip-flop implementation features and their interaction with the combinational environment, which requires dual-rail coding of information signals, and offers effective circuit solutions that ensure the adequacy of their behavior in relation to synchronous counterparts.
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