检索结果-内蒙古大学图书馆

30th Great Lakes Symposium on VLSI, GLSVLSI 2020

作者： Agrawal, Rashmi Bu, Lake Del Rosario, Eliakin Kinsy, Michel A. Adaptive and Secure Computing Systems Laboratory Department of Electrical and Computer Engineering Boston University United States Charles Stark Draper Laboratory Inc. CambridgeMA United States

ISBN: (纸本)9781450379441

Random number generator (RNG) is a core component in many applications such as scientific research, testing and diagnosis, gaming, and cryptosystems (e.g., obfuscation, encryption, and authentication). Although, there are various RNG designs targeting specific application goals such as low-power, high-throughput, stronger security guarantees, a universal programmable RNG design has remained elusive. Indeed, it is a challenge to have only one RNG unit in a system with multiple compute modules with different randomness requirements. In this work, we aim to provide a practical solution to this design challenge by proposing a multi-purpose true random number generator (TRNG), which can be configured in real time to generate random sequences with different requirements. Such a programmable TRNG is able to supply random bits to multiple modules with different demands. The proposed TRNG is a highly convenient multi-purpose hardware primitive that can be deployed in many designs as it provides a tunable physical entropy source and a dynamic cost-performance trade-off. © 2020 Association for computing Machinery.

关键词： Cryptography

来源：评论

学校读者我要写书评

暂无评论

A Hardware Root-of-Trust Design for Low-Power SoC Edge Devices

A Hardware Root-of-Trust Design for Low-Power SoC Edge Devic...

引用

IEEE Conference on High Performance Extreme computing (HPEC)

作者： Alan Ehret Eliakin Del Rosario Karen Gettings Michel A. Kinsy Adaptive and Secure Computing Systems (ASCS) Laboratory Texas A&M University MIT Lincoln Laboratory

ISBN: (数字)9781728192192

ISBN: (纸本)9781728192208

In this work, we introduce a hardware root-of-trust architecture for low-power edge devices. An accelerator-based SoC design that includes the hardware root-of-trust architecture is developed. An example application for the device is presented. We examine attacks based on physical access given the significant threat they pose to unattended edge systems. The hardware root-of-trust provides security features to ensure the integrity of the SoC execution environment when deployed in uncontrolled, unattended locations. E-fused boot memory ensures the boot code and other security critical software is not compromised after deployment. Digitally signed programmable instruction memory prevents execution of code from untrusted sources. A programmable finite state machine is used to enforce access policies to device resources even if the application software on the device is compromised. Access policies isolate the execution states of application and security-critical software. The hardware root-of-trust architecture saves energy with a lower hardware overhead than a separate secure enclave while eliminating software attack surfaces for access control policies.

关键词： Performance evaluation Access control Conferences Automata Computer architecture Hardware Application software

来源：评论

学校读者我要写书评

暂无评论

Design-flow Methodology for secure Group Anonymous Authentication

Design-flow Methodology for Secure Group Anonymous Authentic...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Rashmi Agrawal Lake Bu Eliakin Del Rosario Michel A. Kinsy Adaptive and Secure Computing Systems (ASCS) Laboratory Boston University The Charles Stark Draper Laboratory Cambridge MA

ISBN: (数字)9783981926347

ISBN: (纸本)9781728144689

In heterogeneous distributed systems, computing devices and software components often come from different providers and have different security, trust, and privacy levels. In many of these systems, the need frequently arises to (i) control the access to services and resources granted to individual devices or components in a context-aware manner and (ii) establish and enforce data sharing policies that preserve the privacy of the critical information on end users. In essence, the need is to authenticate and anonymize an entity or device simultaneously, two seemingly contradictory goals. The design challenge is further complicated by potential security problems, such as man-in-the-middle attacks, hijacked devices, and counterfeits. In this work, we present a system design flow for a trustworthy group anonymous authentication protocol (GAAP), which not only fulfills the desired functionality for authentication and privacy, but also provides strong security guarantees.

关键词： Authentication Protocols Privacy Buildings Color Hardware

来源：评论

学校读者我要写书评

暂无评论

A Post-Quantum secure Discrete Gaussian Noise Sampler

A Post-Quantum Secure Discrete Gaussian Noise Sampler

引用

IEEE International Workshop on Hardware-Oriented Security and Trust (HOST)

作者： Rashmi Agrawal Lake Bu Michel A. Kinsy Adaptive and Secure Computing Systems (ASCS) Laboratory Boston University The Charles Stark Draper Laboratory Inc. Cambridge MA

ISBN: (数字)9781728174051

ISBN: (纸本)9781728174068

While the notion of achieving “quantum supremacy” may be debatable, rapid developments in the field of quantum computing are heading towards more realistic quantum computers. As practical quantum computers start becoming more feasible, the requirement to have quantum secure cryptosystems becomes more compelling. Due to its many advantages, lattice based cryptography has become one of the key candidates for designing secure systems for the post-quantum era. The security of lattice-based cryptography is governed by the small error samples generated from a Gaussian distribution. Hence, the Gaussian distribution lies at the core of these cryptosystems. In this paper, we present the hardware design implementation of three different sampling algorithms including rejection, Box-Muller, and the Ziggurat method for the Gaussian Sampler. Our goal is to provide concrete recommendations for future use and adoption in various cryptosystems based on sampling efficiency, hardware cost and throughput. The key feature of our design implementation is that it performs high-precision sampling to meet the NIST's recommended security level of 112-bits or higher for the postquantum era, which most existing hardware implementations fail to do. Furthermore, our design implementation is highly optimized for FPGA-based implementation and is also generic so that it can be seamlessly integrated into most cryptosystems. Synthesis results are obtained using Vivado design suite for a Xilinx Zynq-7010 CLG400ACX1341 FPGA board.

关键词： Security Hardware Cryptography Gaussian distribution Quantum computing Computers Throughput

来源：评论

学校读者我要写书评

暂无评论

HPC I/O Throughput Bottleneck Analysis with Explainable Local Models 20

HPC I/O Throughput Bottleneck Analysis with Explainable Loca...

引用

Supercomputing Conference

作者： Mihailo Isakov Eliakin del Rosario Sandeep Madireddy Prasanna Balaprakash Philip Carns Robert B. Ross Michel A. Kinsy Adaptive and Secure Computing Systems (ASCS) Laboratory Texas A & M University College Station TX Argonne National Laboratory Lemont IL

ISBN: (数字)9781728199986

ISBN: (纸本)9781728199993

With the growing complexity of high-performance computing (HPC) systems, achieving high performance can be difficult because of I/O bottlenecks. We analyze multiple years' worth of Darshan logs from the Argonne Leadership computing Facility's Theta supercomputer in order to understand causes of poor I/O throughput. We present Gauge: a data-driven diagnostic tool for exploring the latent space of supercomputing job features, understanding behaviors of clusters of jobs, and interpreting I/O bottlenecks. We find groups of jobs that at first sight are highly heterogeneous but share certain behaviors, and analyze these groups instead of individual jobs, allowing us to reduce the workload of domain experts and automate I/O performance analysis. We conduct a case study where a system owner using Gauge was able to arrive at several clusters that do not conform to conventional I/O behaviors, as well as find several potential improvements, both on the application level and the system level.

关键词： Leadership Tools Writing Throughput Supercomputers Space exploration Tuning

来源：评论

学校读者我要写书评

暂无评论

Gauge: An Interactive Data-Driven Visualization Tool for HPC Application I/O Performance Analysis

Gauge: An Interactive Data-Driven Visualization Tool for HPC...

引用

IEEE/ACM International Parallel Data systems Workshop (PDSW)

作者： Eliakin del Rosario Mikaela Currier Mihailo Isakov Sandeep Madireddy Prasanna Balaprakash Philip Carns Robert B. Ross Kevin Harms Shane Snyder Michel A. Kinsy Adaptive and Secure Computing Systems (ASCS) Laboratory Texas A&M University College Station TX Argonne National Laboratory Lemont IL

ISBN: (数字)9781665415941

ISBN: (纸本)9781665415958

Understanding and alleviating I/O bottlenecks in HPC system workloads is difficult due to the complex, multilayered nature of HPC I/O subsystems. Even with full visibility into the jobs executed on the system, the lack of tooling makes debugging I/O problems difficult. In this work, we introduce Gauge, an interactive, data-driven, web-based visualization tool for HPC I/O performance analysis. Gauge aids in the process of visualizing and analyzing, in an interactive fashion, large sets of HPC application execution logs. It performs a number of functions met to significantly reduce the cognitive load of navigating these sets - some worth many years of HPC logs. For instance, as its first step in many processing chains, it arranges unordered sets of collected HPC logs into a hierarchy of clusters for later analysis. This clustering step allows application developers to quickly navigate logs, find how their jobs compare to those of their peers in terms of I/O utilization, as well as how to improve their future runs. Similarly, facility operators can use Gauge to `get a pulse' on the workloads running on their HPC systems, find clusters of under performing applications, and diagnose the reason for poor I/O throughput. In this work, we describe how Gauge arrives at the HPC jobs clustering, how it presents data about the jobs, and how it can be used to further narrow down and understand behavior of sets of jobs. We also provide a case study on using Gauge from the perspective of a facility operator.

关键词： Tools Principal component analysis Navigation Visualization Throughput Supercomputers Performance analysis

来源：评论

学校读者我要写书评

暂无评论

Toward Generalizable Models of I/O Throughput

Toward Generalizable Models of I/O Throughput

引用

Runtime and Operating systems for Supercomputers (ROSS), IEEE/ACM International Workshop on

作者： Mihailo Isakov Eliakin del Rosario Sandeep Madireddy Prasanna Balaprakash Philip Carns Robert B. Ross Michel A. Kinsy Adaptive and Secure Computing Systems (ASCS) Laboratory Texas A&M University College Station TX 77843 Argonne National Laboratory Lemont IL 60439

ISBN: (数字)9781665422680

ISBN: (纸本)9781665422697

Many modern HPC applications do not make good use of the limited available I/O bandwidth. Developing an understanding of the I/O subsystem is a critical first step in order to better utilize an HPC system. While expert insight is indispensable, I/O experts are in rare supply. We seek to automate this effort by developing and interpreting models of I/O throughput. Such interpretations may be useful to both application developers who can use them to improve their codes and to facility operators who can use them to identify larger problems in an HPC system. The application of machine learning (ML) to HPC system analysis has been shown to be a promising direction. However, the direct application of ML methods to I/O throughput prediction often leads to brittle models with low extrapolative power. In this work, we set out to understand the reasons why common methods underperform on this specific problem domain, and how to build models that better generalize on unseen data. We show that commonly used cross-validation testing yields sets that are too similar, preventing us from detecting overfitting. We propose a method for generating test sets that encourages training-test set separation. Next we explore limits of I/O throughput prediction and show that we can estimate I/O contention noise by observing repeated runs of an application. Then we show that by using our new test sets, we can better discriminate different architectures of ML models in terms of how well they generalize.

关键词： Data models Throughput Predictive models Training Computational modeling Runtime Mathematical model

来源：评论

学校读者我要写书评

暂无评论

Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codes

Design of reliable storage and compute systems with lightwei...

引用

作者： Bu, Lake Karpovsky, Mark G. Kinsy, Michel A. Adaptive and Secure Computing Systems Laboratory Department of Electrical and Computer Engineering Boston University Boston United States Reliable Computing Laboratory Department of Electrical and Computer Engineering Boston University Boston United States

In this study, the authors propose a new group testing based (GTB) error control codes (ECCs) approach for improving the reliability of memory structures in computing systems. Compared with conventional single- A nd double-bit error correcting codes, the GTB codes provide higher reliability at the multi-byte error correction granularity. The proposed codes are cost-efficient in their encoding and decoding procedures. Instead of requiring multiplication or inversion over Galois finite field like most multi-byte ECC schemes, the proposed technique only involves bitwise XOR operations, therefore, significantly reducing the computation complexity and latency. For instance, to correct m errors in a Q-ary codeword of length N, where $Q \ge 2$Q≥2, the compute complexity is mere $O\lpar mN\log Q\rpar $O(mNlog. âiQ). The GTB codes trade redundancy for encoding and decoding simplicity, and are able to achieve better code rate than other ECCs of the same trade-off. The proposed GTB codes lend themselves well to designs with high reliability and low computation complexity requirements, such as storage systems with strong fault tolerance, or compute systems with straggler tolerance, and so on. © 2019 Institution of Engineering and Technology. All rights reserved.

关键词： Fault tolerance

来源：评论

学校读者我要写书评

暂无评论

Homomorphic Encryption Based secure Sensor Data Processing

Homomorphic Encryption Based Secure Sensor Data Processing

引用

IEEE Conference on High Performance Extreme computing (HPEC)

作者： Vijay Gadepally Mihailo Isakov Rashmi Agrawal Jeremy Kepner Karen Gettings Michel A. Kinsy Lincoln Laboratory Massachusetts Institute of Technology Lexington MA Adaptive and Secure Computing Systems (ASCS) Laboratory Texas A&M University College Station TX Boston University Boston MA

ISBN: (数字)9781728192192

ISBN: (纸本)9781728192208

Novel sensor processing algorithms face many hurdles to their adoption. Sensor processing environments have become increasingly difficult with an ever increasing array of threats. These threats have, in turn, raised the bar on deploying new capabilities. Many novel sensor processing algorithms exploit or induce randomness to boost algorithm performance. Co-designing this randomness with cryptographic features could be a powerful combination providing both improved algorithm performance and increased resiliency. The emerging field of signal processing in the encrypted domain has begun to explore such approaches. The development of this new class of algorithms will require new classes of tools. In particular, the foundational linear algebraic mathematics will need to be enhanced with cryptographic concepts to allow researchers to explore this new domain. This work highlights a relatively low overhead method that uses homomorphic encryption to enhance the resiliency of a part of a larger sensor processing pipeline.

关键词： Pipelines Signal processing algorithms Tools Signal processing Encryption Resilience Sensor arrays

来源：评论

学校读者我要写书评

暂无评论

Post-quantum cryptographic hardware primitives

arXiv

引用

arXiv 2019年

作者： Bu, Lake Agrawal, Rashmi Cheng, Hai Kinsy, Michel A. Adaptive and Secure Computing Systems Laboratory Department of Electrical and Computer Engineering Boston University

The development and implementation of post-quantum cryptosystems have become a pressing issue in the design of secure computing systems, as general quantum computers have become more feasible in the last two years. In this work, we introduce a set of hardware post-quantum cryptographic primitives (PCPs) consisting of four frequently used security components, i.e., public-key cryptosystem (PKC), key exchange (KEX), oblivious transfer (OT), and zero-knowledge proof (ZKP). In addition, we design a high speed polynomial multiplier to accelerate these primitives. These primitives will aid researchers and designers in constructing quantum-proof secure computing systems in the post-quantum era. Copyright © 2019, The Authors. All rights reserved.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：