Let P be a set of n input points in the plane. An algorithm is proposed to place a pair of axis-parallel unit squares, either intersecting with no points in the intersection zone or disjoint, together enclosing the ma...
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With growing demand for complex and high density integrated chips (IC), optical lithography with 193 nm immersion technology has become a bottleneck in the chip manufacturing industry. IC fabrication industry is looki...
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With growing demand for complex and high density integrated chips (IC), optical lithography with 193 nm immersion technology has become a bottleneck in the chip manufacturing industry. IC fabrication industry is looking forward to next generation lithography methods, for example, Extreme Ultraviolet Lithography (EUVL). While EUVL is capable of printing with a wavelength of 13.5 nm, it suffers from a major drawback called flare, due to the scattering of light on blank surfaces. Large flare and/or its large variation cause critical dimension (CD) violations. In this paper, we propose an Integer Linear Programming based method to mitigate the effects of flare in the post routing step through perturbation of wire segments. Experimental results on a set of synthetic circuits show significant reduction of flare and its standard deviation across the chip surface.
While the role of ternary reversible and quantum computation has been growing, synthesis methodologies for such logic, have been addressed in only a few works. A reversible ternary logic function can be expressed as m...
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ISBN:
(纸本)9781479953424
While the role of ternary reversible and quantum computation has been growing, synthesis methodologies for such logic, have been addressed in only a few works. A reversible ternary logic function can be expressed as minterms by using projection operators. In this paper, a novel realization of the projection operators using a minimum number of permutative ternary Muthukrishnan-Stroud (M-S) gates is presented. Next, an efficient method for logic simplification for ternary reversible logic is proposed. This method along with the new construction of projection operators yields significantly lower gate cost of approximately 31% less than that obtained by earlier methodologies, for the synthesis of ternary benchmark circuits.
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