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CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits

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IEICE Transactions on Electronics 2002年第1 SPEC.期E85-C卷 225-229页

作者： Min, Kyeong-Sik Ahn, Jin-Hong Advanced Memory Design Department Memory R and D Division Hynix Semiconductor Inc. 1 Hyangjeong-dong Hungduk-gu Cheongju-si 361-725 Korea Republic of

To overcome the problems of the modified dickson pump like NCP-2, another pump (CCTS-1) where simple voltage doublers are cascaded in series and each of them has cross-coupled configuration is studied in this letter for possible use in low-voltage EEPrOMs and drAMs. Though this concept of cascading doublers has been previously proposed, it is firstly addressed in this letter that CCTS-1 has lower gate-oxide stress, improved voltage pumping gain, and better power efficiency than NCP-2 so that CCTS-1 can be more suitable for multi-stage pump in particular at low VCC. In addition, CCTS-2 is proposed to overcome the degraded body-effect of CCTS-1 without using boosted clocks when the stage number is large.

关键词： MOS devices

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A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth

A reconfigurable multilevel parallel graphics cache memory w...

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Symposium on VLSI circuits

作者： Se-Jeong Park Jeong-Su Kim ramchan Woo Se-Joong Lee Kang-Min Lee Tae-Hum Yang Jin-Yong Jung Hoi-Jun Yoo Department of Electrical Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea Memory R&D Division HYUNDAI Electronics Advanced Circuit Design Team Incheon South Korea

ISBN: (纸本)4891140143

A dedicated single-chip multilevel parallel graphics cache memory for high-speed parallel texture mapping in PC graphics has been fabricated by a 0.16 /spl mu/m drAM technology. The proposed cache architecture is composed of four components: 1) an 8 MB drAM L2 cache, 2) eight 16 KB SrAM L1 parallel caches, 3) eight pipelined texture data filters, 4) serial-to-parallel latches. The refill bandwidth of the parallel L1 cache is maximized up to 75 GB/sec by a hidden double data transfer scheme between the L2 and L1 caches. Furthermore, by adaptive sub-wordline activation scheme, the line sizes of the L2 and L1 caches are reconfigurable for achieving optimal cache miss rate and lower power consumption. The SrAM L1 caches and the texture filters by use of parallel pipelined structures result in higher system performance.

关键词： Graphics Cache memory random access memory Bandwidth Filters Layout Energy consumption System performance Surface texture Pipelines

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Study on coined solder bumps on micro-via PCBs

Study on coined solder bumps on micro-via PCBs

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International Symposium on Electronic Materials and Packaging

作者： Jae-Woong Nah K.W. Paik Won-Hoe Kim Ki-rok Hur Department of Materials Sci. & Engineering Korea Advanced Institute of Science and Technology Daejeon South Korea Circuit R&D Center Samsung Electro Mechanics Company Limited Yeongi Gun Chungcheongnam South Korea Bump 2 Team Microscale Company Limited Pyeongtaek Gyeonggi South Korea

ISBN: (纸本)0780371577

In this study, three solders, Sn-37Pb, Sn-3.5Ag, and Sn3.8-Ag-0.7Cu, were screen printed on both electroless Ni/Au and OSP finished micro-via PCBs. The pad opening size and pitch of micro-via PCB were 120 /spl mu/m and 230 /spl mu/m respectively. The diameter of the screen printed solder bumps was 150 /spl mu/m and the height above the solder mask was 85 /spl mu/m. After that, the solder bumps were coined until 25 /spl mu/m in height by a newly developed coining machine with variable pressure, temperature, and time. The Sn-37Pb solder formed less amounts of intermetallic compounds than all other Pb-free solders on both electroless Ni/Au and OSP (organic solderability preservatives) finished PCBs during solder reflows because of the lower Sn content and lower reflow temperature. For OSP finish, fracture occurred 100% within the solder regardless of reflow numbers. However, for Ni/Au finish, a brittle fracture at the Ni-Sn IMC layer or the interface between the Ni-Sn intermetallic and the P-rich layer was observed after several reflows. The relation of coining load vs. height of coined solder bump showed three stages of coining deformation. Coining loads needed for same height deformation increased as applied coining rate increased. And the planarity of coined solder bump could be increased as the coining rate decreased. As the coining temperature increased, lower coining loads were needed.

关键词： Flip chip Temperature Costs Assembly Printing Surface finishing Gold Intermetallic Packaging Materials science and technology

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Ultra low-power CMOS IC using partially-depleted SOI technology

Ultra low-power CMOS IC using partially-depleted SOI technol...

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Custom Integrated circuits Conference (CICC)

作者： A. Ebina T. Kadowaki Y. Sato M. Yamaguchi Semiconductor Operation Division Seiko Epson Corporation Suwa-gun Nagano Japan Circuit Design Department and IC R&D Department Seiko Epson Corporation Suwa-gun Nagano Japan

We have developed an ultra low power IC for wrist-watch application. The realized operation current and voltage were 30 nA and 0.42 V respectively. This extremely low power operation was achieved by taking full advant... 详细信息

关键词： CMOS integrated circuits CMOS technology Watches Energy consumption Batteries Capacitance Power generation Solar power generation Threshold voltage Application specific integrated circuits

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Contributory presentations/posters

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Journal of Biosciences 1999年第1期24卷 33-198页

作者： N. Manoj V. r. Srinivas A. Surolia M. Vijayan K. Suguna r. ravishankar r. Schwarzenbacher K. Zeth diederichs G. M. Kostner A. Gries P. Laggner r. Prassl Madhusudan Pearl Akamine Nguyen-huu Xuong Susan S. Taylor M. Bidva Sagar K. Saikrishnan S. roy K. Purnapatre P. Handa U. Varshney B. K. Biswal N. Sukumar J. K. Mohana rao A. Johnson Vasantha Pattabhi S. Sri Krishna Mira Sastri H. S. Savithri M. r. N. Murthy Bindu Pillai Kannan M. V. Hosur Mukesh Kumar Swati Patwardhan K. K. Kannan B. Padmanabhaa S. Sasaki-Sugio M. Nukaga T. Matsuzaki S. Karthikevan S. Sharma A. K. Sharma M. Paramasivam P. Kumar J. A. Khan S. Yadav A. Srinivasan T. P. Singh S. Gourinath Neelima Alam A. Srintvasan Vikas Chandra Punit Kaur Ch. Betzel S. Ghosh A. K. Bera S. Bhattacharya S. Chakraborty A. K. Pal B. P. Mukhopadhyay I. dey U. Haldar Asok Baneriee Jozef Sevcik Adriana Solovicova K. Sekar M. Sundaralingam N. Genov dong-cai Liang Tao Jiang Ji-ping Zhang Wen-rui Chang Wolfgang Jahnke Marcel Blommers S. C. Panchal r. V. Hosur Bindu Pillay Puniti Mathur S. Srivatsun ratan Mani Joshi N. r. Jaganathan V. S. Chauhan H. S. Atreya S. C. Sahu K. V. r. Chary Girjesh Govil Elisabeth Adjadj Éric Quinjou Nadia Izadi-Pruneyre Yves Blouquit Joël Mispelter Bernadette Heyd Guilhem Lerat Philippe Milnard Michel desmadreil Y. Lin B. d. Nageswara rao Vidva raghunathan Mei H. Chau Prashant Pesais Sudha Srivastava Evans Coutinho Anil Saran Leizl F. Sapico Jayson Gesme Herbert Lijima raymond Paxton Thamarapu Srikrishnan C. r. Grace G. Nagenagowda A. M. Lynn Sudha M. Cowsik Sarata C. Sahu S. Chauhan A. Bhattacharya G. Govil Anil Kumar Maurizio Pellecchia Erik r. P. Zuiderweg Keiichi Kawano Tomoyasu Aizawa Naoki Fujitani Yoichi Hayakawa Atsushi Ohnishi Tadayasu Ohkubo Yasuhiro Kumaki Kunio Hikichi Katsutoshi Nitta V. rani Parvathy r. M. Kini Takumi Koshiba Yoshihiro Kobashigawa Min Yao Makoto demura Astushi Nakagawa Isao Tanaka Kunihiro Kuwajima Jens Linge Seán O. donoghue Michael Nilges G. Chakshusmathi Girish S. ratnaparkhi P. K. Madhu r. Varadarajan C. Tetreau Molecular Biophysics Unit Indian Institute of Science Bangalore India Austrian Academy of Sciences Institute of Biophysics and X-ray Structure Research Graz Austria Faculty of Biology University of Konstanz Germany Institute of Medical Biochemistry University of Graz Austria Howard Huges Medical Institute Department of Chemistry & Biochemistry University of California La Jolla USA Department of Chemistry & Biochemistry University of California San Diego La Jolla USA Molecular Biophysics Unit India Department of Microbiology &Cell Biology Indian Institute of Science Bangalore India Macromolecular Structure Laboratory NCI - Frederick Cancer Research and Development Center ABL - Basic Research Program Frederick USA Department of Crystallography and Biophysics University of Madras Chennai Biochemistry Department Indian Institute of Science Bangalore India Condensed Matter Physics Division B.A.R.C. Trombay Mumbai Condensed Matter Physics Division Bhabha Atomic Research Centre Trombay Mumbai IMCB The University of Tokyo Tokyo Japan Mitsubishi Chemical Corporation Yokohama Research Center Yokohama Japan Faculty of Pharmaceutical Sciences Chiba University Chiba Japan Department of Biophysics All India Institute of Medical Sciences New Delhi India Department of Biophysics All India Institute of Medical sciences New Delhi India Institüt Physiologische Chemie Hamburg Germany Biophysics Department Bose Institute Calcutta India Slovak Academy of Sciences Institute of Molecular Biology Bratislava Slovakia Indian Institute of Science Bioinformatics Centre Bangalore Departments of Chemistry and Biochemistry Biological Macromolecular Structure Center USA Bulgarian Academy of Sciences Institute of Organic Chemistry Sofia Bulgaria Chinese Academy of Sciences Institute of Biophysics Beijing China Novartis Pharma AG Preclinical Research Basel Switzerland Department of Chemical Sciences Tata Institute of Fundamental Research Mumbai India Solid State Physics Div

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Arsenal ship program certification plan

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NAVAL ENGINEErS JOUrNAL 1998年第1期110卷 249-261页

作者： Arntson, S Lind, W Turner, JJ Blaiklock, WC Tedesco, M Stephen G. Arntson is an independent consultant. A degree Naval Architect he has over 38 years of experience in the design construction and maintenance of surface ships. His experience includes 28 yeus with the Naval Sea Systems Command Naval Ship Engineering Centerl Bureau of Ships specializing in the structural design of Naval surface ships and 7 years with ABS Specializing in the application of commercial ship design practices. Most recently he worked with both NASSCO and ABS MZ the Arsenal Ship Program. Steve was very active with the Ships Structure Committee in developing R&D programs for ship structure and he is a member of the ASNE Journal Committee. Steve received a BS in Mechanical Engineering (Naval Architecture Option) from Virginia Polytechnic Institute in 1964. He is a member of the ASNE TAU BETA PI PI TAU SIGMA and PHI KAPPA PHI. William 1. Lind joined ABS in 1992 after ten years with Sparkman and Stephens Inc. He is currently ABS Amekas Manager of Engineering jm New Orleans and Cleveland. Both ofices conduct plan reviews for militavy commercial and private marine craft fm self-propelled vessels under 300 feet in length and bargus unlimited in length. As Vice-Chaimn ojthe Western Rivers Technical Committee Great Lakes Technical Committee and the Small Vessel Committee Bill participated in the writing of the 1997 ABS Guide for Building and Classing High Speed Craft and the 1997 ABS Rules for Building and Classing Steel Vessels Under 9OM. Bill received an MBA from Florida Atlantic University in 1995 a BS in Mechanical Engineering from New York Institute of Technology in 1986 and a BA in Histoy from Colgate University in 1976. He is Chaimn of SNAME HS-9 Composite Panel Testing & Fire Protection and a member of ASNE. John J. Turner is Senior Vice President of SYNTEK Technologies Inc. in Arlington Virginia. SYNTEK specializes in activities of a highly technical nature supporting both industry and government in domestic and international markets. He is a registered Professional Engineer

The defense advanced research Project Agency (dArPA), in conjunction with the U.S. Navy, initiated a research program for the design and construction of a distinctive warship for the 21st century known as the Arsenal Ship. By using an innovative development and acquisition approach it was hoped to streamline the procurement process and reduce costs. In an environment where budgets are being cut, both industry and Government were challenged to develop, design, and produce the innovative ship and related mission systems to meet specific performance capabilities within strict affordability constraints. A key element of this innovative acquisition approach was a new certification scheme designed to replace the traditional test and evaluation (T&E) and acceptance process. The purpose of this paper is to describe the development of the certification plan during Phase LI of the Arsenal Ship program by the American Bureau of Shipping and the contending Shipyard teams, and to discuss the potential benefits of this alternative certification approach. Although the Arsenal Ship program was canceled late in 1997, insight derived from the exploration of new certification concepts could benefit future design and building programs.

关键词： Warships

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robust estimator design for forward kinematics solution of a Stewart platform

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Journal of Field robotics 1998年第1期15卷

作者： Ji-Yoon Kang dong Hwan Kim Kyo-Il Lee Electro Mechanics Laboratory Samsung Advanced Institute of Technology P.O. Box 111 Suwon 440-600 Korea Industrial Automation Technology R&D Center Mechtronics Research Team Korea Institute of Industrial Technology San 17-1 HongChon-Ri IbJang-Myun ChonAn-Si ChungNam-Do 330-820 Korea Department of Mechanical Design and Production Engineering Seoul National University San 56-1 ShinLim-Dong KwanAk-Gu Seoul Korea

We propose a robust estimator design to solve the forward kinematics in 6 dOF motion bed (Stewart platform). The stability of the proposed estimator is proved via Lyapunov stability analysis and the estimator guarantees practical stability. We introduce the estimator design algorithm which tackles the nonlinearity and uncertainty in the system and present the methods to select estimator gain. The cone-bound condition imposed on the error dynamics is shown and this condition is adopted to prove the stability of the estimator. © 1998 John Wiley & Sons, Inc. 15: 29–42, 1998

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A 3V g/sub M/ C-filter with on-chip tuning for CdMA

A 3V g/sub M/ C-filter with on-chip tuning for CDMA

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Custom Integrated circuits Conference (CICC)

作者： K. Halonen S. Lindfors J. Jussila L. Siren Electronic Circuit Design Laboratory Helsinki University of Technology Espoo Finland R & D Department Nokia Mobile Phones Limited San Diego CA USA

This paper describes a low-voltage channel selection analog front-end with continuous-time filters and on-chip tuning. The filters were realized as balanced seventh order elliptical g/sub m/ C-filters to achieve low current consumption. A novel floating resistor based transconductor was developed to satisfy stringent intermodulation distortion specification and to fulfil the requirement for low supply voltage. A novel biasing for high-swing cascode output stages that extends the practical signal swing capability was developed. A digital tuning circuit based on a time-domain integrator was realized.

关键词： Multiaccess communication Voltage resistors Transconductance Filters Transconductors Feedback loop Mirrors circuit optimization distortion

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advanced double hull structural design technology

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NAVAL ENGINEErS JOUrNAL 1997年第3期109卷 117-127页

作者： Sikora, J Grassman, JM Sensharma, P Watts, J Jerry Sikora:has been with the Naval Surface Warfare Center Carderock Division (NSWCCD) since he received his B.S. degree in physics f r m the University of Detroit in 1969. He is the head of the Design Applications Branch of the Structures and Cmposites Department. Mx Sikora began his career in the field of holographic and other optical measurements of structural parameters. Over the past decade and a half he has developed probability based loads criteria for conventional and SWATH ships. Recently he has been involved in developing structural design criteria and design methods for the cellular structure of advanced double hull ships. Jon M. Grassman:received his B.S. degree in ocean engi-neering from Texas A & M University in 1987. Following graduation he joined the Design Applications Branch at NSWCCD. He has been primarily involved in the application of finite element methods for the design and analysis of naval ships SWATHS and advanced double hull combatant and commercial ships. Pradeep Sensharma:received his B.S. degree in naval architecture from the Indian Institute of Technology Kharagpul: India in 1981. Following that he worked in the Design and Development Section of Mazagon Dock Ltd. Bombay India for five years. He received his M.S. degree in 1988 and his doctoral degree in 1993 from Virginia Polytechnic Institute and State University. Dr. Sensharma specializes in finite element analysis and optimization. He joined Designers & Planners Inc. In 1995. Recently he has been involved In the design and analysis of advanced double hull ships. Joan Watts:is currently the director of naval architecture for Designers & Planners Inc. Arlington Virginia. She graduated from the University of Michigan with a B.S.E. in naval architecture and marine engineering in 1979. Since graduation she has been employed as a naval architect with various consulting firms mainly in the Washington D. C. area.

The Mid-Term Sealift Ship Technology development Program is a multiyear research and development effort to examine promising technologies for application to construction of sealift ships. One of the goals of this program is to enhance the competitiveness of U.S. shipbuilders by investigating a new method of hull construction that would be easier and cheaper to build and preoutfit. The concept consists of a long-spanned, unidirectionally-stiffened structural system where the main structural elements are arranged longitudinally This technology is referred to as advanced double hull (AdH). This paper describes the second year of study in which a new design criterion was applied. This criterion was based upon the results of structural testing and analysis conducted by the Naval Surface Warfare Center Carderock division (NSWCCd) to determine the ultimate strength of cellular structure. A full ship finite element model was developed to help validate the structural criteria.

关键词： Hulls (ship)

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TrANSMISSION-LINE MOdELING OF THE CLASS-E AMPLIFIEr WITH AN ANALYTICAL METHOd

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INTErNATIONAL JOUrNAL OF NUMErICAL MOdELLING-ELECTrONIC NETWOrKS dEVICES ANd FIELdS 1995年第5期8卷 357-366页

作者： YAM, YO CHEUNG, CW LI, CH Department of Electronic Engineering City University of Hong Kong 83 Tat Chee Avenue Kowloon Tong Hong Kong Yu On Yam (Yu-An Ren) graduated from the South China University of Technology Guanzhou china with B. Eng. (EE) and Ph.D. in engineering. he served in the Department of Microwave Electronics Research Institute of Electronics Academia Sinica Beijing China as researcher assoicate professor and full professor. He was awarded a gold medal by the State Commission of Science and Technology PR China in 1985 for his achievement in R&D works. He was also elected as fellow of CIE (the chinese Institute of Electronics). He served briefly in the Institut fur Hochfrequenztechnik TH Darmstadt and Alexander von Humboldt Stiftung of West Germany as a visting professor in 1980–82. In 1986 he returned to Hong Kong where he was born. He joined the Department of Electronic Engineering City University of Hong Kong (formerly known as City Polytechnic of Hong Kong) where he has been ever since. His research interests and publications are in the field of RF and microwave electronics RF circuit design and development and microwave communication engineering. Chi-Hung Li graduated with the B.Eng. (Hons) degree in electronic engineering from City Polytechnic of Hong Kong in 1991 and then the M.Phil. degree in electronic engineering from City University of Hong Kong in 1994. His research interests are RF circuit design simulation and mobile communication engineering.

The transmission line modelling (TLM) technique was used to simulate the class E power amplifier. An analytical method is also used to fix the required component values to ensure the desired output performance of the ... 详细信息

关键词： Transmission line theory

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