This paper presents a preliminary PhD research towards developing a framework to evaluate and optimize application mapping algorithms for Network-on-Chip architectures. Several such algorithms have been proposed for m...
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ISBN:
(纸本)9781424473359
This paper presents a preliminary PhD research towards developing a framework to evaluate and optimize application mapping algorithms for Network-on-Chip architectures. Several such algorithms have been proposed for mapping the threads of a parallel application on a NoC architecture. However, the performance of those algorithms is evaluated only on some specific NoC designs. A unified approach for evaluating such algorithms allows a better comparison of their performance and can potentially lead to some optimizations. The proposed framework is intended to be flexible so that the algorithms can be tested on different NoC designs. To this end, a scalable and flexible Network-on-Chip simulator is proposed. Some preliminary results obtained with this simulator are presented, too. They show the flexibility of this simulator and that it is feasible for addressing the application mapping problem in a unified manner.
作者：
Miyazaki, JYokota, HMemberSchool of Information Science
Japan Advanced Institute of Science and Technology Ishikawa-ken Japan 923 Received his B.E. degree from Tokyo Institute of Technology
Tokyo Japan in 1992 and his M.S. degree from Japan Advanced Institute of Science and Technology (JAIST) Ishikawa Japan in 1994. He is a Ph.D. student at School of Information Science JAIST. His research interests include parallel rule base systems active database systems and high performance I/O systems. He is a member of the Institute of Electronics Information and Communication Engineers of Japan and Information Processing Society of Japan.Received his B.E.
M.E. and Dr. of Eng. degrees from Tokyo Institute of Technology in 1980 1982 and 1991 respectively. He joined Fujitsu Ltd. in 1982 and was a researcher at the Institute of New Generation Computer Technology (ICOT) from 1982 to 1986 and at Fujitsu Laboratories Ltd. from 1986 to 1992. He is an Associate Professor of School of Information Science Japan Advanced Institute of Science and Technology (JAIST). HIS research interests include parallel computer architecture for databases and data engineering. He is a member of IPS I.E.I.C.E.JSAIIEEEand ACM.
An implementation method is proposed for parallel production systems on multicomputers, or message-passing computers, to speed up execution time. There have been proposed parallel production systems using hash mechani...
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An implementation method is proposed for parallel production systems on multicomputers, or message-passing computers, to speed up execution time. There have been proposed parallel production systems using hash mechanism, but they cause a skewed load distribution problem. To obtain more efficient balance of load, the method addressed here and named clustered parallel production systems (CPPS) adopts two load balancing strategies: hash and demand-driven. Taking account of the cost of termination detection, the execution time of the CPPS and simple hash method are estimated, and implement on an nCube2. The estimation meets the execution results. The CPPS provides much better load balance to improve scalability.
作者：
NACHTSHEIM, JOHN J.BALLOU, L. DENNISJohn J. Nachtsheim:is currently the Deputy Assistant Administrator for Research & Development for the Maritime Administration. His duties are the planning
coordinating organizing evaluating and directing of the R&D activities of MarAd. His past experiences include: Naval Architect for the Naval Ship Engineering Center 1959 Deputy Chief Design Engineer for the Puget Sound Naval Shipyard
1958 to 1959 and Naval Architect
the former Bureau of Ships 1948 to 1958. His education is comprised of a B.S. degree from the Webb Institute of Naval Architecture an L.L.B. degree from the George Washington University Law School completion of the Advanced Management Program at Harvard University and current study of Transportation at the American University. He is a Registered Professional Engineer in the District of Columbia and a Member of the Bar in the District of Columbia and the State of Maryland. In addition to ASNE his other professional memberships include the Society of Naval Architects and Marine Engineers the Society of Aeronautical Weight Engineers and the Association of Senior Engineers of the Naval Ships Systems Command (Honorary). USNCommander L. Dennis Ballou:
USN is the Head of the Engineering Service Office Naval Ship Engineering Center. He is involved in computer hardware and software services to support engineering design automatic data processing systems design work study and quality assurance. Prior to NavSec duty Commander Ballou served in various billets afloat and ashore: tours on the USS Skagit and Tang supervision of the USS Skipjack's first overhulconstruction of the USS Nathanael Greene and helping to establish the Polaris overhaul program. He is a graduate of the U.S. Naval Academy
Officers' Submarine School and the Webb Institute of Naval Architecture. He holds BS and MS degrees in marine engineering and naval architecture respectively. He has also completed many graduate
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