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Optimizing application mapping algorithms for NoCs through a unified framework

Optimizing application mapping algorithms for NoCs through a...

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作者： Radu, Ciprian Vintan, Lucian Advanced Computer Architecture and Processing Systems Research Lab. Lucian Blaga University Sibiu Romania

ISBN: (纸本)9781424473359

This paper presents a preliminary PhD research towards developing a framework to evaluate and optimize application mapping algorithms for Network-on-Chip architectures. Several such algorithms have been proposed for mapping the threads of a parallel application on a NoC architecture. However, the performance of those algorithms is evaluated only on some specific NoC designs. A unified approach for evaluating such algorithms allows a better comparison of their performance and can potentially lead to some optimizations. The proposed framework is intended to be flexible so that the algorithms can be tested on different NoC designs. To this end, a scalable and flexible Network-on-Chip simulator is proposed. Some preliminary results obtained with this simnlator are presented, too. They show the flexibility of this simulator and that it is feasible for addressing the application mapping problem in a unified manner.

关键词： Network-on-chip

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An automatic design space exploration framework for multicore architecture optimizations

An automatic design space exploration framework for multicor...

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Roedunet International Conference (RoEduNet)

作者： Horia Calborean Lucian Vinţan Advanced Computer Architecture & Processing Systems Research Lab “Lucian Blaga” University of Sibiu Romania

ISBN: (纸本)9781424473359

During the last years, especially due to the computing systems complexity growth, the need for tools which perform automatic design space exploration becomes more and more stringent. This paper presents a new initiated project having as the main aim developing a software tool, called FADSE (Framework for Automatic Design Space Exploration), that comes to meet this need. It is intended to provide out-of-the-box algorithms capable of solving single and multiobjective optimization problems. It focuses on automatic design space exploration for multicore and manycore systems. This tool is intended to be flexible, to provide easy development and portability.

关键词： Space exploration Multicore processing Design optimization computer architecture Ant colony optimization Microarchitecture Software tools Software design Heuristic algorithms Machine learning algorithms

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Optimizing application mapping algorithms for NoCs through a unified framework

Optimizing application mapping algorithms for NoCs through a...

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Roedunet International Conference (RoEduNet)

作者： Ciprian Radu Lucian Vinţan Advanced Computer Architecture & Processing Systems Research Lab “Lucian Blaga” University of Sibiu Romania

ISBN: (纸本)9781424473359

This paper presents a preliminary PhD research towards developing a framework to evaluate and optimize application mapping algorithms for Network-on-Chip architectures. Several such algorithms have been proposed for mapping the threads of a parallel application on a NoC architecture. However, the performance of those algorithms is evaluated only on some specific NoC designs. A unified approach for evaluating such algorithms allows a better comparison of their performance and can potentially lead to some optimizations. The proposed framework is intended to be flexible so that the algorithms can be tested on different NoC designs. To this end, a scalable and flexible Network-on-Chip simulator is proposed. Some preliminary results obtained with this simulator are presented, too. They show the flexibility of this simulator and that it is feasible for addressing the application mapping problem in a unified manner.

关键词： Network-on-a-chip Algorithm design and analysis Application software Routing Tiles computer architecture Testing Network topology Design optimization

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Analysis of hardware prefetching across virtual page boundaries

Analysis of hardware prefetching across virtual page boundar...

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4th Conference On Computing Frontiers 2007

作者： Dreslinski, Ronald G. Saidi, Ali G. Mudge, Trevor Reinhardt, Steven K. Advanced Computer Architecture Lab. Department of Electrical Engineering and Computer Science 2260 Hayward Ave Ann Arbor MI 48109-2121 United States Reservoir Labs Inc.

ISBN: (纸本)1595936831

Data cache prefetching in the L2 is at the forefront of pre-fetching research. In this paper we analyze the impact of virtual page boundaries on these prefetchers. Conservative measurements on real hardware show that 30-50% of consecutive virtual pages are mapped to pages which are not consecutive in physical memory. advanced hardware prefetching techniques that detect access patterns which span virtual page boundaries often end up prefetching data that is from the wrong physical page. Meanwhile, current simulation techniques for evaluating prefetching algorithms assume that all virtual pages are mapped consecutively. We show that not accounting for virtual page boundaries in simulation can lead to overestimates of as much as 29% (9% on average). We also show that a simple prefetch filter can improve performance up to 32% (7% on average) and recover the overestimated performance. This leads to the conclusion that although previous simulations may not have accounted for virtual page boundaries, the results they demonstrate are still attainable and that it is not necessary to simulate virtual page boundaries to get accurate results. However, actual hardware designers should take care to implement a simple filter or else their hardware may not show the same gains in performance as they did in simulation. Copyright 2007 ACM.

关键词： Virtual reality

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Reliability-aware data placement for partial memory protection in embedded processors 06

Reliability-aware data placement for partial memory protecti...

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2006 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, MSPC 2006

作者： Mehrara, Mojtaba Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595935789

Low cost protection of embedded systems against soft errors has recently become a major concern. This issue is even more critical in memory elements that are inherently more prone to transient faults. In this paper, we propose a reliability aware data placement technique in order to partially protect embedded memory systems. We show that by adopting this method instead of traditional placement schemes with complete memory protection, an acceptable level of fault tolerance can be achieved while incurring less area and power overhead. In this approach, each variable in the program is placed in either protected or non-protected memory area according to the profile-driven liveness analysis of all memory variables. In order to measure the level of fault coverage, we inject faults into the memory during the course of program execution in a Monte Carlo simulation framework. Subsequently, we calculate the coverage of partial protection scheme based on the number of protected, failed and crashed runs during the fault injection experiment. Copyright 2006 ACM.

关键词： Program processors

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Ultra low-cost defect protection for microprocessor pipelines

Ultra low-cost defect protection for microprocessor pipeline...

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作者： Shyam, Smitha Constantinides, Kypros Phadke, Sujay Bertacco, Valeria Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595934510

The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Silicon failure mechanisms, such as transistor wearout and manufacturing defects, are a growing challenge that threatens the yield and product lifetime of future systems. In this paper we introduce the BulletProof pipeline, the first ultra low-cost mechanism to protect a microprocessor pipeline and on-chip memory system from silicon defects. To achieve this goal we combine area-frugal on-line testing techniques and system-level checkpointing to provide the same guarantees of reliability found in traditional solutions, but at much lower cost. Our approach utilizes a microarchitectural checkpointing mechanism which creates coarse-grained epochs of execution, during which distributed on-line built in self-test (BIST) mechanisms validate the integrity of the underlying hardware. In case a failure is detected, we rely on the natural redundancy of instructionlevel parallel processors to repair the system so that it can still operate in a degraded performance mode. Using detailed circuit-level and architectural simulation, we find that our approach provides very high coverage of silicon defects (89%) with little area cost (5.8%). In addition, when a defect occurs, the subsequent degraded mode of operation was found to have only moderate performance impacts, (from 4% to 18% slowdown). Copyright © 2006 ACM.

关键词： Microprocessor chips

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Cost-efficient soft error protection for embedded microprocessors

Cost-efficient soft error protection for embedded microproce...

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CASES 2006: International Conference on Compilers, architecture and Synthesis for Embedded Systems

作者： Blome, Jason A. Gupta, Shantanu Feng, Shuguang Mahlke, Scott Bradley, Daryl Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI ARM Ltd. Cambridge United Kingdom

ISBN: (纸本)1595935436

Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety critical applications, ranging from automobiles to pacemakers, compounds the importance of addressing the soft error problem. Historically, soft error tolerance techniques have been targeted mainly at high-end server markets, leading to solutions such as coarse-grained modular redundancy and redundant multithreading. However, these techniques tend to be prohibitively expensive to implement in the embedded design space. To address this problem, we first present a thorough analysis of the effects of soft errors on a production-grade, fully synthesized implementation of an ARM926EJ-S embedded microprocessor. We then leverage this analysis in the design of two orthogonal low-costs of terror protection techniques that can be tuned to achieve variable levels of fault coverage as a function of area and power constraints. The first technique uses a small cache of live register values in order to provide nearly twice the fault coverage of a register file protected using traditional error correcting codes at little or no additional area cost. The second technique is a statistical method used to significantly reduce the overhead of deploying time-delayed shadow latches for low-latency fault detection. Copyright 2006 ACM.

关键词： Error detection

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Scalable subgraph mapping for acyclic computation accelerators

Scalable subgraph mapping for acyclic computation accelerato...

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CASES 2006: International Conference on Compilers, architecture and Synthesis for Embedded Systems

作者： Clark, Nathan Hormati, Amir Mahlke, Scott Yehia, Sami Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI ARM Ltd. Cambridge United Kingdom

ISBN: (纸本)1595935436

computer architects are constantly faced with the need to improve performance and increase the efficiency of computation in their designs. To this end, it is increasingly common to see acyclic com-putation accelerators appear in embedded processor designs. One major problem with adding accelerators to a design is that it is difficult to generate high-quality code utilizing them. Hand-written assembly code is typical, and if compiler support does exist, it is implemented using only greedy algorithms. In this work, we investigate more thorough techniques for compiling to processors with acyclic accelerators. Where as greedy solutions only explore one possible solution, the techniques presented in this paper explore the entire design space, when possible. Intelligent pruning methods are employed to ensure compilation is both tractable and scalable. Overall, our new compilation algorithms produce code that performs on average 10%, and up to 32% better than standard greedy methods. These algorithms also run in less than one second for more than 98% of basic blocks tested. Copyright 2006 ACM.

关键词： Conformal mapping

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Integrated network interfaces for high-bandwidth TCP/IP

Integrated network interfaces for high-bandwidth TCP/IP

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作者： Binkert, Nathan L. Saidi, Ali G. Reinhardt, Steven K. Advanced Computer Architecture Lab. Department of Electrical Engineering and Computer Science University of Michigan Hewlett-Packard Labs. Reservoir Labs Inc.

ISBN: (纸本)1595934510

This paper proposes new network interface controller (NIC) designs that take advantage of integration with the host CPU to provide increased flexibility for operating system kernel-based performance *** believe that this approach is more likely to meet the needs of current and future high-bandwidth TCP/IP networking on end hosts than the current trend of putting more complexity in the NIC, while avoiding the need to modify applications and protocols. This paper presents two such NICs. The first, the simple integrated NIC (SINIC), is a minimally complex design that moves the responsibility for managing the network FIFOs from the NIC to the kernel. Despite this closer interaction between the kernel and the NIC, SINIC provides performance equivalent to a conventional DMA-based NIC without increasing CPU overhead. The second design, V-SINIC, adds virtual per-packet registers to SINIC, enabling parallel packet processing while maintaining a FIFO model. V-SINIC allows the kernel to decouple examining a packet's header from copying its payload to memory. We exploit this capability to implement a true zero-copy receive optimization in the Linux 2.6 kernel, providing bandwidth improvements of over 50% on unmodified sockets-based receive-intensive benchmarks. Copyright © 2006 ACM.

关键词： Interfaces (computer)

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STACCATO: Disjoint support decompositions from BDDs through symbolic kernels

STACCATO: Disjoint support decompositions from BDDs through ...

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2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

作者： Plaza, Stephen Bertacco, Valeria Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI United States

ISBN: (纸本)0780387368

A disjoint support decomposition (DSD) is a representation of a Boolean function F obtained by composing two or more simpler component functions such that the component functions have no common inputs. The decomposition of a function is desirable for several reasons. First, it's a method to obtain a multiple-levei implementation of a function. It leads to a partition in simpler blocks that easily results in smaller areas and fewer interconnects. Moreover, it exposes a parallelism in the computation of the function that can be exploited by hardware as well as during simulation. In this paper we present a novel algorithm, STACCATO, that generates a DSD decomposition stai-ting from the BDD of a function. STACCATO is novel because 1) it provides a complete description of each decomposition, that is, it computes the "kernel" function K relating the elements of each decomposition, and 2) it has better performance than previously known algorithms. Experimental results run on both IWLS and industrial test-benches show that STACCATO'S performance is in most cases three times as fast or more than previously known solutions. © 2005 IEEE.

关键词： Boolean functions

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