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How to fake 1000 registers 38

How to fake 1000 registers

引用

MICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Oehmke, David W. Binkert, Nathan L. Mudge, Trevor Reinhardt, Steven K. Advanced Computer Architecture Lab. University of Michigan Ann Arbor Cray Inc.

ISBN: (纸本)0769524400

Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading). Support for both of these together requires a multiplicative number of registers that quickly becomes prohibitive. We overcome this limitation with the virtual context architecture (VGA), a new register-file architecture that virtualizes logical register contexts. VCA works by treating the physical registers as a cache of a much larger memory-mapped logical register space. Complete contexts, whether activation records or threads, are no longer required to reside in their entirety in the physical register file. A VCA implementation of register windows on a single-threaded machine reduces data cache accesses by 20%, providing the same performance as a conventional machine while requiring one fewer cache port. Using VCA to support multithreading enables a four-thread machine to use half as many physical registers without a significant performance loss. VCA naturally extends to support both multithreading and register windows, providing higher performance with significantly fewer registers than a conventional machine. © 2005 IEEE.

关键词： computer architecture

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Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

Total power reduction in CMOS circuits via gate sizing and m...

引用

42nd Design Automation Conference, DAC 2005

作者： Gao, Feng Hayes, John P. Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48105 United States

Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt's are common ways to meet power and timing budgets. We propose an automatic implementation of both these techniques using a mixed-integer linear programming model called MLP-exact, which minimizes a circuit's total active-mode power consumption. Unlike previous linear programming methods which only consider local optimality, MLP-exact can find a true global optimum. An efficient, non-optimal way to solve the MLP model, called MLP-fast, is also described. We present a set of benchmark experiments which show that MLP-fast is much faster than MLP-exact, while obtaining designs with only slightly higher power consumption. Furthermore, the designs generated by MLP-fast consume 30% less power than those obtained by conventional, sensitivity-based methods. Copyright 2005 ACM.

关键词： CMOS integrated circuits

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Drowsy region-based caches: Minimizing both dynamic and static power dissipation

Drowsy region-based caches: Minimizing both dynamic and stat...

引用

2005 Computing Frontiers Conference

作者： Geiger, Michael J. McKee, Sally A. Tyson, Gary S. Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109-2122 Computer Systems Lab. Cornell University Ithaca NY 14853-3801 Department of Computer Science Florida State University Tallahassee FL 32306-4530

ISBN: (纸本)1595930183

Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal partitioning reduces average power per data access by employing multiple smaller structures or using cache subbanks. For instance, region-based caching places small caches dedicated to stack and global accesses next to the LI data cache. With respect to static power dissipation, leakage power may be addressed at both circuit and architectural levels. Drowsy caches reduce leakage power by keeping inactive lines in a low-power mode. Here we merge drowsy and region-based caching to reduce overall cache power consumption, showing that the combination yields more benefits than either alone. Applications from the MiBench suite exhibit power reductions in the cache system of up to 68-71%, depending on memory configuration, with a small increase in execution time. Copyright 2005 ACM.

关键词： Buffer storage

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Beyond basic region caching: Specializing cache structures for high performance and energy conservation

引用

1st International Conference on High Performance Embedded architectures and Compilers, HiPEAC 2005

ISBN: (纸本)3540303170

Increasingly tight energy design goals require processor architects to re-think the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Embedded systems

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Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

Total power reduction in CMOS circuits via gate sizing and m...

引用

Design Automation Conference

作者： Feng Gao J.P. Hayes Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

ISBN: (纸本)1595930582

Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different V/sub t/'s are common ways to meet power and timing budgets. We propose an automatic implementation of both these techniques using a mixed-integer linear programming model called MLP-exact, which minimizes a circuit's total active-mode power consumption. Unlike previous linear programming methods which only consider local optimality, MLP-exact can find a true global optimum. An efficient, non-optimal way to solve the MLP model, called MLP-fast, is also described. We present a set of benchmark experiments which show that MLP-fast is much faster than MLP-exact, while obtaining designs with only slightly higher power consumption. Furthermore, the designs generated by MLP-fast consume 30% less power than those obtained by conventional, sensitivity-based methods.

关键词： Circuits Threshold voltage Energy consumption Linear programming Algorithm design and analysis Permission Capacitance Delay lines Piecewise linear approximation Space exploration

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StressTest: an automatic approach to test generation via activity monitors

StressTest: an automatic approach to test generation via act...

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Design Automation Conference

作者： I. Wagner V. Bertacco T. Austin Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

The challenge of verifying a modern microprocessor design is an overwhelming one: increasingly complex micro-architectures combined with heavy time-to-market pressure have forced microprocessor vendors to employ immense verification teams in the hope of finding the most critical bugs in a timely manner. Unfortunately, too often size doesn't seem to matter for verification teams, as design schedules continue to slip and microprocessors find their way to the marketplace with design errors. In this paper, we describe a simulation-based random test generation tool, called StressTest, that provides assistance in locating hard-to-find corner-case design bugs and performance problems. StressTest is based on a Markov-model-driven random instruction generator with activity monitors. The model is generated from the user-specified template programs and is used to generate the instructions sent to the design under test (DUT). In addition, the user specifies key activity points within the design that should be stressed and monitored throughout the simulation. The StressTest engine then uses closed-loop feedback techniques to transform the Markov model into one that effectively stresses the points of interest. In parallel, StressTest monitors the correctness of the DUT response to the supplied stimuli, and if the design behaves unexpectedly, a bug and a trace that leads to it are reported. Using two micro-architectures as example testbeds, we demonstrate that StressTest finds more bugs with less effort than open-loop random instruction test generation techniques.

关键词： Automatic testing Microprocessors computer bugs Analytical models Formal verification computer displays Permission Logic testing computer architecture Processor scheduling

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A Family of Logical Fault Models for Reversible Circuits

A Family of Logical Fault Models for Reversible Circuits

引用

Asian Test Symposium (ATS)

作者： I. Polian T. Fiehn B. Becker J.P. Hayes Georges-Köhler-Allee 51 Albert Ludwig University Freiburg im Breisgau Germany Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional circuits such as stuck-at models are not wellsuited to quantum circuits. We derive a family of logical fault models for reversible circuits composed of k- CNOT (k-input controlled-NOT) gates and implementable by many technologies. The models are extensions of the previously proposed single missing-gate fault (MGF) model, and include multiple and partial MGFs. We study the basic detection requirements of the new fault types and derive bounds on the size of their test sets. We also present optimal test sets computed via integer linear programming for various benchmark circuits. These results indicate that, although the test sets are generally very small, partial MGFs may need significantly larger test sets than single MGFs.

关键词： Circuit faults Quantum computing Circuit testing Quantum mechanics Physics computing computer architecture Power dissipation Computational modeling Electrical fault detection Fault detection

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Gate sizing and Vt assignment for active-mode leakage power reduction

Gate sizing and Vt assignment for active-mode leakage power ...

引用

Proceedings - IEEE International Conference on computer Design: VLSI in computers and Processors, ICCD 2004

作者： Gao, Feng Hayes, John P. Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109 United States

Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduce leakage power. We assume a standard-cell-based design flow where the available cell sizes and threshold voltages (V t's) are given, and model the optimization as a mixed-integer linear programming (MLP) problem. In addition to the exact model, two faster approximate MLP models are proposed, along with CAD tools that generate the models automatically. We present experimental results which show that optimal designs derived from the exact MLP model can achieve the same performance as all-low-Vt unit-size designs, but with only one third the leakage power. The approximate MLP models can be solved about 25 times faster than the optimal model with negligible errors. All the proposed models can be extended to take dynamic power and multiple supply voltages into consideration. © 2004 IEEE.

关键词： Leakage currents

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Microarchitectural Power Modeling Techniques for Deep Sub-Micron Microprocessors

Microarchitectural Power Modeling Techniques for Deep Sub-Mi...

引用

2004 International Symposium on Low Power Electronics and Design, ISLPED 2004

作者： Kim, Nam Sung Kgil, Taeho Bertacco, Valeria Austin, Todd Mudge, Trevor Microprocessor Research Intel Labs HillsboroOR97124 United States Advanced Computer Architecture Lab University of Michigan Ann ArborMI48109 United States

ISBN: (纸本)1581139292

The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance has moved to the fore. To satisfy this demand several microarchitectural power simulators have been developed around SimpleScalar, a widely used microarchitectural performance simulator. They have proven to be very useful at providing insights into power/performance trade-offs. However, they are neither parameterized nor technology scalable. In this paper, we propose more accurate parameterized power modeling techniques reflecting the actual technology parameters as well as input switching-events for memory and execution units. Compared to HSPICE, the proposed techniques show 93% and 91% accuracies for those blocks, but with a much faster simulation time. We also propose a more realistic power modeling technique for external I/O. In general, our approach includes more detailed microarchitectural and circuit modeling than has been the case in earlier simulators, without incurring a significant simulation time overhead-it can be as small as a few percent. © 2004 ACM.

关键词： Simulators

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Reducing pipeline energy demands with local DVS and dynamic retiming

Reducing pipeline energy demands with local DVS and dynamic ...

引用

International Symposium on Low Power Electronics and Design (ISLPED)

作者： Seokwoo Lee S. Das T. Pham T. Austin D. Blaauw T. Mudge Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

The quadratic relationship between voltage and energy has made dynamic voltage scaling (DVS) one of the most powerful techniques to reduce system power demands. Recently, techniques such as Razor DVS, voltage overscaling, and intelligent energy management have emerged as approaches to further reduce voltage by eliminating costly voltage margins inserted into traditional designs to ensure always-correct operation. The degree to which a global voltage controller can shave voltage margins is limited by imbalances in pipeline stage latency. Since all pipeline stages share the same voltage, the stage exercising the longest critical path will define the overall voltage of the system, even if other stages could potentially run at lower voltages. In this paper, we evaluate two local tuning mechanisms in the context of Razor DVS, a local voltage controller scheme that allows each pipeline stage its own voltage level, and a lower cost dynamic retiming scheme that incorporates per-stage clock delay elements to allow longer-latency pipeline stages to "borrow" time from shorter-latency stages. Using simulation, we draw two key insights from our study. First, mitigating pipeline stage imbalances render additional DVS energy savings. A Razor pipeline design with dynamic retiming finds an additional 12% energy savings over global voltage control (resulting in overall energy savings of more than 28% compared to fully-margined DVS). Second, we demonstrate that imbalances arise not only from design factors, but also from run-time characteristics. As the program (or program phase) changes, we see different logic paths in multiple stages exercised frequently, necessitating a dynamic fine-tuning of local control. This result suggests that even well-balanced pipelines could benefit from dynamic retiming.

关键词： Pipelines Voltage control Dynamic voltage scaling Power demand Energy management Costs Clocks Delay effects Runtime Logic

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