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Proceedings -31st Annual International Symposium on computer architecture

作者： Weaver, Christopher Emer, Joel Mukherjee, Shubhendu S. Reinhardt, Steven K. Massachusetts Microproc. Des. Ctr. Intel Corporation 77 Reed Road Hudson MA 01749 Advanced Computer Architecture Lab. EECS Department University of Michigan 1301 Beal Avenue Ann Arbor MI 48109

Transient faults due to neutron and alpha particle strikes pose a significant obstacle to increasing processor transistor counts in future technologies. Although fault rates of individual transistors may not rise significantly, incorporating more transistors into a device makes that device more likely to encounter a fault. Hence, maintaining processor error rates at acceptable levels will require increasing design effort. This paper proposes two simple approaches to reduce error rates and evaluates their application to a microprocessor instruction queue. The first technique reduces the time instructions sit in vulnerable storage structures by selectively squashing instructions when long delays are encountered. A fault is less likely to cause an error if the structure it affects does not contain valid instructions. We introduce a new metric, MTTF (Mean Instructions To Failure), to capture the trade-off between performance and reliability introduced by this approach. The second technique addresses false detected errors. In the absence of a fault detection mechanism, such errors would not have affected the final outcome of a program. For example, a fault affecting the result of a dynamically dead instruction would not change the final program output, but could still be flagged by the hardware as an error. To avoid signalling such false errors, we modify a pipeline's error detection logic to mark affected instructions and data as possibly incorrect rather than immediately signaling an error. Then, we signal an error only if we determine later that the possibly incorrect value could have affected the program's output.

关键词： Microprocessor chips

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Microarchitectural power modeling techniques for deep sub-micron microprocessors

Microarchitectural power modeling techniques for deep sub-mi...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Nam Sung Kim T. Kgil V. Bertacco T. Austin T. Mudge Microprocessor Research INTEL Research Laboratory Hillsboro OR USA Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance has moved to the fore. To satisfy this demand several microarchitectural power simulators have been developed around SimpleScalar, a widely used microarchitectural performance simulator They have proven to be very useful at providing insights into power/performance trade-offs. However, they are neither parameterized nor technology scalable. In this paper, we propose more accurate parameterized power modeling techniques reflecting the actual technology parameters as well as input switching-events for memory and execution units. Compared to HSPICE, the proposed techniques show 93% and 91% accuracies for those blocks, but with a much faster simulation time. We also propose a more realistic power modeling technique for external I/O. In general, our approach includes more detailed microarchitectural and circuit modeling than has been the case in earlier simulators, without incurring a significant simulation time overhead - it can be as small as a few percent.

关键词： Microarchitecture Microprocessors Table lookup Circuit simulation Integrated circuit modeling Energy consumption Batteries Permission Power dissipation computer architecture

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Self-optimization in computer systems via on-line control: application to power management

Self-optimization in computer systems via on-line control: a...

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International Conference on Autonomic Computing (ICAC)

作者： N. Kandasamy S. Abdelwahed J.P. Hayes Institute for Software Integrated Systems Vanderbilt University Nashville TN USA Advanced Computer Architecture Lab EECS Depaartment University of Michigan Ann Arbor MI USA

computer systems hosting critical e-commerce applications must typically satisfy stringent quality-of-service (QoS) requirements under dynamic operating conditions and workloads. Also, as such systems increase in size and complexity, maintaining the desired QoS by manually tuning the numerous performance-related parameters will become very difficult. This paper addresses the design of self-optimizing computer systems using a generic online control framework in which the control actions governing the operation of the system are obtained by optimizing its behavior, as forecast by a mathematical model, over a limited time horizon. As a specific application of this control technique, we show how to minimize the power consumed by a single computer processing a time-varying workload. Assuming a processor capable of operating at multiple frequencies, we design an online controller to satisfy the QoS requirements of the workload while operating the processor at the lowest possible frequency. We describe the processor model, formulate the power management problem, and derive the online control algorithm. The performance of the controller is evaluated using representative e-commerce workloads. Finally, we discuss how the proposed technique can be applied to other resource management problems in computer systems.

关键词： Control systems Application software Energy management Power system management Frequency Quality of service Design optimization Mathematical model Power system modeling Resource management

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Architectural optimizations for low-power, real-time speech recognition

Architectural optimizations for low-power, real-time speech ...

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CASES 2003: International Conference on Compilers, architecture, and Synthesis for Embedded Systems

作者： Krishna, Rajeev Mahlke, Scott Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor United States

ISBN: (纸本)1581136765

The proliferation of computing technology to low power domains such as hand-held devices has lead to increased interest in portable interface technologies, with particular interest in speech recognition. The computational demands of robust, large vocabulary speech recognition systems, however, are currently prohibitive for such low power devices. This work begins an exploration of domain specific characteristics of speech recognition that might be exploited to achieve the requisite performance within the power constraints of such devices. We focus primarily on architectural techniques to exploit the massive amounts of potential thread level parallelism apparent in this application domain, and consider the performance / power trade-offs of such architectures. Our results show that a simple, multi-threaded, multi-pipelined processor architecture can significantly improve the performance of the time-consuming search phase of modern speech recognition algorithms, and may reduce overall energy consumption by drastically reducing dissipation of static power. We also show that the primary hurdle to achieving these performance benefits is the data request rate into the memory system, and consider some initial solutions to this problem. Copyright 2003 ACM.

关键词： Speech recognition

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Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches

Leakage Power Optimization Techniques for Ultra Deep Sub-Mic...

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IEEE/ACM International Conference on computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers

作者： Kim, Sung Nam Blaauw, David Mudge, Trevor Advanced Computer Architecture Lab Department of Electrical Eng. University of Michigan Ann Arbor

On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming the dominant fraction of the total power consumption of those caches. In this paper, we present optimization techniques to reduce the leakage power of on-chip caches assuming that there are multiple threshold voltages, VTH's, available. First, we show a cache leakage optimization technique that examines the trade-off between access time and leakage power by assigning distinct VTH's to each of the four main cache components - address bus drivers, data bus drivers, decoders, and SRAM cell arrays with sense-amps. Second, we show optimization techniques to reduce the leakage power of L1 and L2 on-chip caches without affecting the average memory access time. The key results are: 1) 2 VTH's are enough to minimize leakage in a single cache;2) if L1 size is fixed, increasing the L2 size can result in much lower leakage without reducing average memory access time;3) if L2 size is fixed, reducing L1 size can result in lower leakage without loss of the average memory access time;and 4) smaller L1 and larger L2 caches than are typical in today's processors result in significant leakage and dynamic power reduction without affecting the average memory access time.

关键词： Cache memory

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Remembrance of data passed: A study of disk sanitization practices

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IEEE Security and Privacy 2003年第1期1卷 17-27页

作者： Garfinkel, Simson L. Shelat, Abhi Massachusetts Inst. of Technology Cryptography/Info. Security Group Advanced Network Architecture Group MIT's Lab. for Computer Science Theory of Computation Group Massachusetts Inst. of Technology

The disk sanitization practices are studied. computer systems used by people with varying authorization levels typically employ authentication, access control lists, and a privileged operating system to maintain information privacy. The study indicates that the secondary hard-disk market is almost certainly awash in information that is both sensitive and confidential. If sanitization practices are not significantly improved, it is only a matter of time before the confidential information on repurposed hard drives is exploited by individuals and organizations that would do us harm.

关键词： Security of data

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Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch

Reducing Register Ports Using Delayed Write-Back Queues and ...

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2003 International Conference on Supercomputing

作者： Kim, Nam Sung Mudge, Trevor Advanced Computer Architecture Lab University of Michigan 1301 Beal Ave. Ann Arbor MI 48109-2122 United States

In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these parameters grow superlinearly as read and write ports are added to support wide-issue. This paper presents techniques to reduce the number of ports of a register file intended for a wide-issue microprocessor without noticeably impacting its IPC. Our results show that it is possible to replace the 16 read/8 write port file of an eight-issue processor with an 8 read/8 write port file so that the impact on IPC is insignificant. This is accomplished with the addition of some small auxiliary memory structures. Furthermore, the access time of the smaller file plus the auxiliary structures is such that if it were the critical path a 45-50% increase in clock speed would be possible. Finally, there is an energy per access savings of about 20% and an area savings of 40%, which has the potential for further savings by shortening global interconnect in the layout. An extension to the scheme that reduces the number of write ports from 8 to 6 is also presented. It suffers modest penalty in terms of IPC, but shows further reduction in energy and area. Depending on implementation characteristics it could yield a further increase in performance.

关键词： Microprocessor chips

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Razor: A low-power pipeline based on circuit-level timing speculation 36

Razor: A low-power pipeline based on circuit-level timing sp...

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36th International Symposium on Microarchitecture, MICRO 2003

作者： Ernst, D. Kim, Nam Sung Das, S. Pant, S. Rao, R. Pham, Toan Ziesler, C. Blaauw, D. Austin, T. Flautner, K. Mudge, T. Advanced Computer Architecture Lab. University of Michigan 1301 Beal Ave Ann ArborMI48109 United States ARM Ltd. 110 Fulbourn Road CambridgeCB1 9NJ United Kingdom

ISBN: (纸本)076952043X

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 μm technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%). © 2003 IEEE.

关键词： Pipelines

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Dependable communication synthesis for distributed embedded systems

Dependable communication synthesis for distributed embedded ...

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22nd International Conference on computer Safety, Reliability and Security, SAFECOMP 2003

作者： Kandasamy, Nagarajan Hayes, John P. Murray, Brian T. Institute for Software Integrated Systems Vanderbilt University NashvilleTN United States Advanced Computer Architecture Lab University of Michigan Ann ArborMI United States The Delphi Corporation BrightonMI United States

ISBN: (纸本)9783540201267

Embedded control applications such as drive-by-wire in cars require dependable interaction between various sensors, processors, and actuators. This paper addresses the design of low-cost communication networks guaranteeing to meet both the performance and fault-tolerance requirements of such distributed applications. We develop a fault-tolerant allocation and scheduling method which maps messages on to a minimum-cost multiplebus system to ensure predictable inter-processor communication. The proposed method targets time-division multiple access (TDMA) communication protocols, and is applicable to protocols such as FlexRay and TTP which have recently emerged as networking standards for embedded systems such as automobile controllers. Finally, we present a case study involving some advanced automotive control applications to show that our approach uses the available network bandwidth efficiently to achieve jitter-free message transmission. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Time division multiple access

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A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor 36

A systematic methodology to compute the architectural vulner...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： S.S. Mukherjee C. Weaver J. Emer S.K. Reinhardt T. Austin VSSAD MMDC Intel Corporation Shrewsbury MA USA Advanced Computer Architecture Lab EECS Department University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780769520438

Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transients faults exist, but come at a cost. Designers clearly require accurate estimates of processor error rates to make appropriate cost/reliability tradeoffs. This paper describes a method for generating these estimates. A key aspect of this analysis is that some single-bit faults (such as those occurring in the branch predictor) do not produce an error in a program's output. We define a structure's architectural vulnerability factor (AVF) as the probability that a fault in that particular structure do not result in an error. A structure's error rate is the product of its raw error rate, as determined by process and circuit technology, and the AVF. Unfortunately, computing AVFs of complex structures, such as the instruction queue, can be quite involved. We identify numerous cases, such as prefetches, dynamically dead code, and wrong-path instructions, in which a fault do not affect, correct execution. We instrument a detailed 1A64 processor simulator to map bit-level microarchitectural state to these cases, generating per-structure AVF estimates. This analysis shows AVFs of 28% and 9% for the instruction queue and execution units, respectively, averaged across dynamic sections of the entire CPU2000 benchmark suite.

关键词： Microprocessors Circuit faults Error analysis Costs computer aided instruction Fault diagnosis Prefetching Instruments Computational modeling Circuit simulation

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