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检索条件"机构=Advanced Computer Architecture Lab"

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Efficient dynamic scheduling through tag elimination

Efficient dynamic scheduling through tag elimination

引用

29th Annual International Symposium on computer architecture

作者： Ernst, Dan Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann Arbor MI 48109 United States

An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of the scheduler can be improved by decreasing the number of tag comparisons necessary to schedule instructions. Using detailed simulation-based analyses, we find that most instructions enter the window with at least one of their input operands already available. By putting these instructions into specialized windows with fewer tag comparators, load capacitance on the scheduler critical path can be reduced, with only very small effects on program throughput. For instructions with multiple unavailable operands, we introduce a last-tag speculation mechanism that eliminates all remaining tag comparators except those for the last arriving input operand. By combining these two tag-reduction schemes, we are able to construct dynamic schedulers with approximately one quarter of the tag comparators found in conventional designs. Conservative circuit-level timing analyses indicate that the optimized designs are 20-45% faster and require 10-20% less power, depending on instruction window size.

关键词： Associative storage

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A Markov chain sequence generator for power macromodeling 02

A Markov chain sequence generator for power macromodeling

引用

IEEE/ACM International Conference on computer Aided Design (ICCAD)

作者： Liu, Xun Papaefthymiou, Marios C. Advanced Computer Architecture Lab. Dept. of Electrical Engineering University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9780780376076

In this paper, we present a novel sequence generator based on a Markov chain model. Specifically, we formulate the problem of generating a sequence of vectors with given average input probability p, average transition density d, and spatial correlation s as a transition matrix computation problem, in which the matrix elements are subject to constraints derived from the specified statistics. We also give a practical heuristic that computes such a matrix and generates a sequence of l n-bit vectors in O(nl+n2) time. Derived from a strongly mixing Markov chain, our generator yields binary vector sequences with accurate statistics, high uniformly, and high randomness. Experimental results show that our sequence generator can cover more than 99% of the parameter space. Sequences of 2,000 48-bit vectors are generated in less than 0.05 seconds, with average deviations of the signal statistics p, d, and s equal to 1.6%, 1.8%, and 2.8%, respectively. Our generator enables the detailed study of power macromodeling. Using our tool and the ISCAS-85 benchmark circuits, we have assessed the sensitivity of power dissipation to the three input statistics p, d, and s. Our investigation reveals that power is most sensitive to transition density, while only occasionally exhibiting high sensitivity to signal probability and spatial correlation. Our experiments also show that input signal imbalance can cause estimation errors as high as 100% in extreme cases, although errors are usually within 25%.

关键词： Markov processes

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Incorporation of input glitches into power macromodeling

Incorporation of input glitches into power macromodeling

引用

2002 IEEE International Symposium on Circuits and Systems

作者： Liu, Xun Papaefthymiou, Marios C. Advanced Computer Architecture Lab Dept. of Elec. Eng. and Comp. Sci. University of Michigan Ann Arbor MI 48109 United States

Previous research on power macromodeling has always assumed glitch-free input signals. However, in an actual operating environment, the input signals of a circuit can contain glitches, which are generated by the previous stage of circuitry. In this paper, we investigate the impact of input glitches on the power dissipation of a circuit. Specifically, we show that the frequency and average duration of input glitches are two important factors affecting the overall power consumption. Input glitches can also increase output glitching by a surprisingly large amount. We present a simple yet effective analytical power macromodeling approach incorporating the effects of input glitching. In experiments with the ISCAS-85 benchmark circuits, the average error of the proposed technique is 4.44%.

关键词： CMOS integrated circuits

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Energy recovering static memory

Energy recovering static memory

引用

Proceedings of the 2002 International Symposium on Low Power Electronics and Design

作者： Kim, Joohee Ziesler, Conrad H. Papaefthymiou, Marios C. Advanced Computer Architecture Lab. Dept. of Elec. Eng. and Comp. Sci. University of Michigan Ann Arbor MI 48109 United States

This paper proposes an energy-recovering (a.k.a. adiabatic) static RAM with a novel driver that reduces power dissipation by efficiently recovering energy from the bit/word line capacitors. Powered by a single-phase sinusoidal power-clock, our SRAM delivers read and write operations with single-cycle latency. To that end, a precharge-low scheme is employed along with a modified sense amplifier design that achieves high efficiency at differential voltages near VSS. A simple control circuit is used to maintain driver operation in synchrony with the power-clock waveform. Feedback circuitry from the driver output to the control circuit ensures that our driver remains efficient, independent of the access pattern. Our energy recovering SRAM functions correctly while achieving substantial energy savings over a wide range of supply voltages and operating frequencies. Hspice simulations of a simple full-custom adiabatic 256×256 SRAM, that includes the energy recovering bit/word line drivers, the cell array, and the sense amplifiers, show over 2.6x energy savings at 3V, 300MHz in comparison with its conventional counterpart.

关键词： Power electronics

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Design of a high-throughput low-power IS95 Viterbi decoder

Design of a high-throughput low-power IS95 Viterbi decoder

引用

39th Design Automation Conference, DAC 2002

作者： Liu, Xun Papaefthymiou, Marios C. Advanced Computer Architecture Lab. Dept. of Elec. Eng. and Comp. Sci. University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)1581134614

The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data-transfer oriented design methodology to implement a low-power 256-state rate-1/3 IS95 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the RTL implementation of the individual processors, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 μm standard cell library, our decoder achieves a throughput of 20 Mbps in simulation and dissipates only 450 mW.

关键词： Decoding

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Drowsy caches: simple techniques for reducing leakage power

Drowsy caches: simple techniques for reducing leakage power

引用

Annual International Symposium on computer architecture, ISCA

作者： K. Flautner Nam Sung Kim S. Martin D. Blaauw T. Mudge ARM Ltd Cambridge UK Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA The University of Michigan Advanced Computer Architecture Lab Ann Arbor MI

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink the dominant component of this power loss will be leakage. However, during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving, low-power drowsy mode. Moving lines into and out of drowsy state incurs a slight performance loss. In this paper we investigate policies and circuit techniques for implementing drowsy caches. We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. According to our projections, in a 0.07 um CMOS process, drowsy caches will be able to reduce the total energy (static and dynamic) consumed in the caches by 50%-75%. We also argue that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.

关键词： Dynamic voltage scaling Voltage control Energy consumption computer architecture Circuit simulation Threshold voltage Leakage current Inverters Semiconductor device modeling Predictive models

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Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction 35

Drowsy instruction caches. Leakage power reduction using dyn...

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35th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2002

作者： Kim, Nam Sung Flautner, Krisztian Blaauw, David Mudge, Trevor Advanced Computer Architecture Lab University of Michigan 1301 Beal Ave. Ann ArborMI48109-2122 United States ARM Ltd 110 Fulboum Road CambridgeCB1 9NJ United Kingdom

ISBN: (纸本)0769518591

On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. In our previous work we have shown how the drowsy circuit - a simple, state-preserving, low-leakage circuit that relies on voltage scaling for leakage reduction - can be used to reduce the total energy consumption of data caches by more than 50%. In this paper, we extend the architectural control mechanism of the drowsy cache to reduce leakage power consumption of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. To enable drowsy instruction caches, we propose a technique called cache sub-bank prediction which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low leakage drowsy mode. This prediction technique reduces the negative performance impact by 76% compared to the no-prediction policy. Our technique works well even with small predictor sizes and enables an 86% reduction of leakage energy in a 64 K byte instruction cache. © 2002 IEEE.

关键词： Tellurium

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Application specific architectures: A recipe for fast, flexible and power efficient designs 2

Application specific architectures: A recipe for fast, flexi...

引用

2nd International Conference on Compilers, architecture, and Synthesis for Embedded Systems, CASES 2001

作者： Weaver, Chris Krishna, Rajeev Wu, Lisa Austin, Todd Advanced Computer Architecture Lab. University of Michigan Ann ArborMI United States

ISBN: (纸本)1581133995

The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent evidence suggests that these efforts may be faltering as pipelining and ILP processing techniques experience diminishing returns. Application specific architectures hold great potential as an alternative means to continue scaling application performance. The approach works by specializing a design to a small domain of important applications, and it benefits from improved performance, greater power efficiency, and reduced area costs. This technique is well matched to embedded targets, where application domains are typically narrow. In this paper we present a case study of an application specific processor design. Our design, called the CryptoManiac processor, is an architecture specialized to efficiently execute cryptographic ciphers. We carefully highlight the domain specific application characteristics we identified and their accompanying optimizations in the CryptoManiac design. Detailed analyses of the design makes a strong case for application specific optimization. The CryptoManiac processor runs popular ciphers at twice the speed of a high-end general purpose processor, and the design renders nearly two orders-ofmagnitude reduction in power consumption and area costs. Finally, we identify two key challenges that stand as barriers to wide spread adoption of application specific architectures. Copyright 2001 ACM.

关键词： Cost reduction

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Integrating superscalar processor components to implement register caching 01

Integrating superscalar processor components to implement re...

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2001 International Conference on Supercomputing

作者： Postiff, M. Greene, D. Raasch, S. Mudge, T. Advanced Computer Architecture Lab. University of Michigan 1301 Beal Ave. Ann Arbor MI 48109-2122 United States

ISBN: (纸本)9781581134100

A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical register file can be slow, particularly in the context of a wide-issue processor which requires an even larger physical register file, and many read and write ports. Previous work has suggested that a register cache can be used to address this problem. This paper proposes a new register caching mechanism in which a number of good features from previous approaches am combined with existing out-of-order processor hardware to implement a register cache for a large logical register file. It does so by separating the logical register file from the physical register file and using a modified form of register renaming to make the cache easy to implement. The physical register file in this configuration contains fewer entries than the logical register file and is designed so that the physical register file acts as a cache f or the logical register file, which is the backing store. The tag information in this caching technique is kept in the register alias table and the physical register file. It is found that the caching mechanism improves IPC up to 20% over an un-cached large logical register file and has performance near to that of a logical register file that is both large and fast.

关键词： Shift registers

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Improving BTB performance in the presence of DLLs 33

Improving BTB performance in the presence of DLLs

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Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

作者： Stevan Vlaovic Edward S. Davidson Gary S. Tyson Advanced Computer Architecture Lab The University of Michigan

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