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Proceedings of the International Conference on Compilers, architecture, and Synthesis for Embedded Systems (CASES 2000)

作者： Lee, Hsien-Hsin S. Tyson, Gary S. Advanced Computer Architecture Lab Elec. Eng./Comp. Science Department University of Michigan Ann Arbor MI United States

ISBN: (纸本)1581133383

Power consumption has been a major concern in designing microprocessors for portable systems such as notebook computers, hand-held computing and personal telecommunication devices. As these devices increase in popularity and are used in a wider range of applications, a low power design becomes more critical. In this paper, we propose a new microarchitectural data cache design called region-based caching that can reduce power consumption. Power savings is achieved by re-organizing the the first level cache to more efficiently exploit memory reference characteristics produced by programming language semantics. These characteristics enable the cache to be partitioned by memory region (stack, global, heap), reducing power consumption, while retaining comparable performance to a conventional cache design. Applications from the MediaBench benchmark suite indicate that a design with two additional small region-based caches results in 66% reduction in average in energy-delay product.

关键词： Embedded systems

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Register queues: a new hardware/software approach to efficient software pipelining

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： M. Smelyanskiy G.S. Tyson E.S. Davidson Advanced Computer Architecture Lab University of Michigan USA

In this paper we propose a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected register space from the physical registers. Using RQs, the compiler can allocate physical registers to store live values in the software pipelined loop while minimizing the pressure placed on architected registers. We show that decoupling the architected register space from the physical register space can greatly increase the applicability of software pipelining, even as memory latencies increase. Res combine the major aspects of existing rotating register file and register connection techniques to generate efficient software pipeline schedules. Through the use of RQs, we can minimize the register pressure and code expansion caused by software pipelining. We demonstrate the effect of incorporating register queues and software pipelining with 983 loops taken from the Perfect Club, the SPEC suites, and the Livermore Kernels.

关键词： Hardware Pipeline processing Registers Delay computer architecture Kernel Optimizing compilers Degradation Throughput

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Near-optimum hierarchical layout synthesis of two-dimensional CMOS cells

Near-optimum hierarchical layout synthesis of two-dimensiona...

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International Conference on VLSI Design

作者： A. Gupta J.P. Hayes Cadence Design Systems Inc. San Jose CA USA Advanced Computer Architecture Lab Dept of EECS University of Michigan Ann Arbor MI USA

We present a hierarchical technique HCLIP to generate near-optimum layouts of CMOS cells in the two-dimensional (2-D) style. HCLIP is based on integer-linear programming and extends our previously published CLIP technique to much larger cells and to 2-D cell-arrays. HCLIP partitions the circuit into clusters, generates minimum-width 1-D placements (chain covers) for each cluster and then selects one cover for each cluster such that the overall 2-D cell width and height is minimized. In doing so, HCLIP explores all diffusion sharing between transistor chains belonging to the selected covers. For width minimization, HCLIP yields 2-D layouts that have minimum width with respect to the given set of covers. For both width and height minimization, since HCLIP is approximate and can overestimate cell height, we analyze the theoretical worst-case approximation. Experimental results demonstrate that HCLIP still yields near-optimal layouts in most cases.

关键词： Minimization Wires Bridge circuits computer architecture Inverters

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Timing analysis using propositional satisfiability

Timing analysis using propositional satisfiability

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5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998

作者： E Silva, Luís Guerra Silva, João P. Marques Silveira, Luís Miguel Sakallah, Karem A. Cadence European Laboratories INESC Institute Superior Técnico R. Alves Redol 9 Lisboa1000 Portugal Electrical Engineering and Computer Science Dept. Advanced Computer Architecture Lab. University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0780350081

The existence of false paths represents a significant and computationally complex problem in the timing analysis of combinational and sequential circuits. In this paper we describe Propositional Satisfiability based algorithms for timing analysis, which introduce significant performance improvements over existing procedures. In particular, we address the problems of circuit delay computation and path delay validation, describing algorithms and providing experimental results for both problems. © 1998 IEEE.

关键词： Timing circuits

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A virtual-physical on-chip cache for shared memory multiprocessors

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3rd International Conference on Parallel Processing, Euro-Par 1997

作者： Kim, Dongwook Lee, Joonwon Computer Architecture Lab. Computer Science Department Korea Advanced Institute of Science and Technology 373-1 Kusung-dong Yusung-ku Taejon 305-701 Korea Republic of

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Width minimization of two-dimensional CMOS cells using integer programming 96

Width minimization of two-dimensional CMOS cells using integ...

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Proceedings of the 1996 IEEE/ACM international conference on computer-aided design

作者： Avaneendra Gupta John P. Hayes Advanced Computer Architecture Lab. Dept. of Electrical Engr. and Computer Science The University of Michigan Ann Arbor MI and Design Technology Division Intel Corporation 2200 Mission College Blvd. Santa Clara CA Advanced Computer Architecture Lab. Dept. of Electrical Engr. and Computer Science The University of Michigan Ann Arbor MI

ISBN: (纸本)9780818675973

We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Run-times for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.

关键词： CMOS networks

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Software error classification using purify

Software error classification using purify

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Proceedings of the 1996 IEEE Conference on Software Maintenance, ICSM

作者： Owens, Howard D. Womack, Baxter F. Gonzalez, Mario J. Motorola Advanced Computer Architecture Lab Austin TX United States

Perfect quality represents 100% conformance to specifications. Complex systems make it difficult and expensive to assure conformance to specifications by post production testing alone. As a result quality assurance processes are moving upstream in the life cycle, i.e., statistical process control and design for manufacturability. These processes try to avoid defects or make it easier to detect defects. In software systems this move to upstream processes for quality control is still in its early stages. As with more traditional manufacturing systems, maturity of the software design and development process will dramatically reduce the cost of attaining conformance to specifications. Even so, it is difficult to imagine a 'bug free' complex software system. Downstream processes will continue to play an important part in the efforts to achieve defect-free software. This paper presents results of a survey which used the defect detection tool Purify to examine off-the-shelf software products in order to show that software errors continue to escape testing and threaten field failures. Errors detected are compiled and presented. All data were collected on C and C++ programs running in a UNIX operating system environment.

关键词： Software engineering

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The trading function in action 7

The trading function in action

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7th Workshop on ACM SIGOPS European Workshop: Systems Support for Worldwide Applications, EW 1996

作者： Jacob, Bruce Mudge, Trevor Advanced Computer Architecture Lab EECS Department University of Michigan United States

ISBN: (纸本)9781450373395

This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed computing and supports a number of application types on different hardware configurations. This paper is the result of lessons learned in the process of designing, building, and modifying an industrial telecommunications platform. In particular, the use of the trading function in the design of the system led to such benefits as support for the dynamic evolution of the system, the ability to dynamically add services and data types to a running system, support for heterogeneous systems, and a simple design performing well enough to handle traffic in excess of 40,000 busy-hour calls.

关键词： Commerce

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Optimal local register allocation for a multiple-issue machine 94

Optimal local register allocation for a multiple-issue machi...

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Proceedings of the 1994 International Conference on Supercomputing

作者： Meleis, W.M. Davidson, E.S. Advanced Computer Architecture Lab Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI

ISBN: (纸本)9780897916653

This paper presents an algorithm that allocates registers optimally for straight-line code running on a generic multi-issue computer. On such a machine, an optimal register allocation is one that minimizes the number of issue slots that the code requires. Optimal spill selection and load/store placement are used to minimize the number of additional issue slots needed, given a schedule for the non-memory reference instructions and a fixed number of available physical registers. The generic multi-issue machine model closely models the operation of vector and VLIW processors, and could be extended to model super-scalar processors. The algorithm uses dynamic programming to search the state space of feasible register allocations; implicit and explicit state pruning are used to make the problem tractable without sacrificing optimality. The optimal allocation produced by the algorithm for a substantial example is presented.

关键词： Dynamic programming

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ANALYTICAL TRANSIENT-RESPONSE OF CMOS INVERTERS

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS 1992年第1期39卷 42-44页

作者： KAYSSI, AI SAKALLAH, KA BURKS, TM Advanced Computer Architecture Lab Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A general formula relating the waveform at the output of a CMOS inverter to the waveform at its input is derived. The formula is applied to three cases: a step input, a ramp input, and an exponential input. A one-dimensional functional dependence of the inverter propagation delay and output slew rate on circuit parameters is derived and an inverter macromodel for timing analysis is suggested and experimentally verified.

关键词： Transient analysis Transient response Inverters Semiconductor device modeling Circuits Capacitance Timing Space exploration Signal design MOS devices

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