检索结果-内蒙古大学图书馆

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： T.M. Austin Advanced Computer Architecture Laboratory University of Michigan USA

Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To further complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation interference. In this paper, we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. The functional checker verifies the correctness of the core processor's computation, only permitting correct results to commit. Overall design cost can be dramatically reduced because designers need only verify the correctness of the checker unit. We detail the DIVA checker architecture, a design optimized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA checkers have little impact on core processor performance. To make the case for reduced verification costs, we argue that the DIVA checker should lend itself to functional and electrical verification better than a complex core processor. Finally, future applications that leverage dynamic verification to increase processor performance and availability are suggested.

关键词： Microarchitecture Microprocessors Cost function Buildings Fabrication Degradation Logic Interference Pipelines computer architecture

来源：评论

学校读者我要写书评

暂无评论

Does low-power design imply energy efficiency for data centers? 11

Does low-power design imply energy efficiency for data cente...

引用

International Symposium on Low Power Electronics and Design (ISLPED)

作者： David Meisner Thomas F. Wenisch Advanced Computer Architecture Laboratory University of Michigan USA

ISBN: (纸本)9781612846606

Data center efficiency has quickly become a first-class design goal. In response, many studies have emerged from the academic community and industry using low-power design to help improve the energy efficiency of server hardware. Generally, these proposals hold the assumption that low-power design is inherently better for energy efficiency; this preconception stems mostly from great success in the mobile space with building low-power, energy-efficient systems. We observe that unlike mobile devices, constraining a data center server to a low power budget is arbitrary and higher power design choices can be more energy efficient. We analyze the energy efficiency design space of past commercial server designs and find that high-power servers are generally more energy efficient than low-power ones. Furthermore, we evaluate building low- or high-power server clusters and find that the small increase in the cost of cooling high-powered servers is easily outweighed by their greater efficiency.

关键词： Servers Dynamic range Cooling Correlation Sockets Atmospheric modeling Industries

来源：评论

学校读者我要写书评

暂无评论

Towards a scalable data center-level evaluation methodology

Towards a scalable data center-level evaluation methodology

引用

IEEE International Symposium on Performance Analysis of Systems and Software

作者： David Meisner Junjie Wu Thomas F. Wenisch Advanced Computer Architecture Laboratory University of Michigan USA

As the popularity of Internet services continues to rise, the need to understand the design of the data center systems hosting these workloads becomes increasingly important. Unfortunately, research in this area has been stifled, primarily due to a lack of tools, workloads, and rigorous evaluation methodology. Traditional tools, such as architectural simulators, do not directly address data center-level issues and do not scale to simulate the thousands of machines needed for data center research. We introduce, Stochastic Queuing Simulation (SQS), our methodology for characterization and evaluation of data center systems. By leveraging techniques from stochastic modeling, queuing theory and statistical sampling, SQS uses discrete-event simulation to drive models that scale to tens of thousands of machines. Whereas detailed architectural simulations can last hours or days, SQS turnaround time is typically on the order of tens of minutes to an hour. Furthermore, computation can be distributed across cores and machines, achieving speedup using commodity clusters.

关键词： Servers Data models Computational modeling Stochastic processes Queueing analysis Instruments Analytical models

来源：评论

学校读者我要写书评

暂无评论

Efficient execution of augmented reality applications on mobile programmable accelerators

Efficient execution of augmented reality applications on mob...

引用

IEEE International Conference on Field-Programmable Technology (FPT)

作者： Jason Jong Kyu Park Yongjun Park Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan USA

Mobile devices are ubiquitous in daily lives. From smartphones to tablets, customers are constantly demanding richer user experiences through more visual and interactive interface with prolonged battery life. To meet the demands, accelerators are commonly adopted in system-on-chip (SoC) for various applications. Coarse-grained reconfigurable architecture (CGRA) is a promising solution, which accelerates hot loops with software pipelining. Although CGRAs have shown that they can support multimedia applications efficiently, more interactive applications such as augmented reality put much more pressure on performance and energy requirements. In this paper, we extend heterogeneous CGRA to provide SIMD capabilities, which improves performance and energy efficiency significantly for augmented reality applications. We show that if we can exploit data level parallelism (DLP), it is more beneficial to run on SIMD natively than to transform it into instruction level parallelism (ILP) and run on CGRA. To utilize this property, multiple processing elements in CGRA are grouped to form homogeneous SIMD cores. To reduce the hardware overhead of fetching and replicating configuration in SIMD mode, we propose a ring network and a recycle buffer to pass the configuration around as well as to temporarily store it, which has minimized impact on throughput. Also, we modify memory access units and memory banks to support split memory transactions with forwarding for handling SIMD data access. To adapt to the proposed extension, we introduce a compile technique for SIMD mode code generation to maximize the resource utilization of each SIMD core. Experimental results show that it is possible to achieve an average of 17.6% performance improvement while saving 16.9% energy over heterogeneous CGRA.

关键词： Software Recycling Augmented reality Acceleration computer architecture Schedules Buffer storage

来源：评论

学校读者我要写书评

暂无评论

A fault tolerant approach to microprocessor design

A fault tolerant approach to microprocessor design

引用

International Conference on Dependable Systems and Networks (DSN)

作者： C. Weaver T. Austin Advanced Computer Architecture Laboratory University of Michigan USA

We propose a fault-tolerant approach to reliable microprocessor design. Our approach, based on the use of an online checker component in the processor pipeline, provides significant resistance to core processor design errors and operational faults such as supply voltage noise and energetic particle strikes. We show through cycle-accurate simulation and timing analysis of a physical checker design that our approach preserves system performance while keeping area overheads and power demands low. Furthermore, analyses suggest that the checker is a fairly simple state machine that can be formally verified, scaled in performance, and reused. Further simulation analyses show virtually no performance impacts when our simple checker design is coupled with a high-performance microprocessor model. Timing analyses indicate that a fully synthesized unpipelined 4-wide checker component in 0.25 /spl mu/m technology is capable of checking Alpha instructions at 288 MHz. Physical analyses also confirm that costs are quite modest; our prototype checker requires less than 6% the area and 1.5% the power of an Alpha 21264 processor in the same technology. Additional improvements to the checker component are described which allow for improved detection of design, fabrication and operational faults.

关键词： Fault tolerance Microprocessors Performance analysis Analytical models Timing Pipelines Process design Voltage System performance Power demand

来源：评论

学校读者我要写书评

暂无评论

Paragon: Collaborative speculative loop execution on GPU and CPU 5

Paragon: Collaborative speculative loop execution on GPU and...

引用

5th Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU-5 - Held in Cooperation with ACM ASPLOS XVII

作者： Samadi, Mehrzad Hormati, Amir Lee, Janghaeng Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States Microsoft Research Microsoft Inc. Redmond WA United States

ISBN: (纸本)9781450312332

The rise of graphics engines as one of the main parallel platforms for general purpose computing has ignited a wide search for better programming support for GPUs. Due to their non-traditional execution model, developing applications for GPUs is usually very challenging, and as a result, these devices are left under-utilized in many commodity systems. Several languages, such as CUDA, have emerged to solve this challenge, but past research has shown that developing applications in these languages is a daunting task because of the tedious performance optimization cycle or inherent algorithmic characteristics of an application, which could make it unsuitable for GPUs. Also, previous approaches of automatically generating optimized parallel code in CUDA for GPUs using complex compilation techniques have failed to utilize GPUs that are present in everyday computing devices such as laptops and mobile systems. In this work, we take a different approach. Although it is hard to generate optimized code for GPU, it is beneficial to utilize them speculatively rather than leaving them running idle due to their high raw performance capabilities compared to CPUs. To achieve this goal, we propose Paragon: a collaborative static/dynamic compiler platform to speculatively run possibly-data-parallel pieces of sequential applications on GPUs. Paragon utilizes the GPU in an opportunistic way for loops that are categorized as possibly-data-parallel by its loop classification phase. While running the loop speculatively, Paragon monitors the dependencies using a light-weight kernel management unit, and transfers the execution to the CPU in case a conflict is detected. Paragon resumes the execution on the GPU after the dependency is executed sequentially on the CPU. Our experiments show that Paragon achieves up to 12x speedup compared to unsafe CPU execution with 4 threads. © 2012 ACM.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

A New Reconfigurable Network Node Processor architecture for Distributed Implementation of Ephemeral State Processing 22

A New Reconfigurable Network Node Processor Architecture for...

引用

22nd International Conference on Parallel and Distributed Computing and Communication Systems, PDCCS 2009

作者： Heath, J. Robert Lim, Nien Yi Calvert, Kenneth L. Griffioen, James Computer Architecture Laboratory Dept. of Electrical and Computer Engineering College of Engineering University of Kentucky LexingtonKY40506 United States Advanced Networking Laboratory Dept. of Computer Science College of Engineering University of Kentucky LexingtonKY40506 United States

ISBN: (纸本)9781615675777

Ephemeral State Processing (ESP) has been proposed as a lightweight, router-based, scalable building block supporting the construction of new and diverse end-to-end network management and other services. Each node of an ESP enhanced network would require a processor for implementation of the ESP service. An overview and background of ESP is first provided. ESP may be implemented within ESP enhanced network nodes three ways: one way is by a high performance special purpose programmable processor architecture best-fit for ESP implemented to reconfigurable Programmable Logic Device (PLD) technology. This implementation approach is addressed in this manuscript. The manuscript focus is the development, design, implementation, validation and evaluation of a most recently developed special purpose programmable Ephemeral State Processor (ESPR) microarchitecture for the implementation of ESP. Advantages of implementing ESPRs to in-field upgradeable reconfigurable platforms are addressed. A hardware prototype of the newly proposed ESPR microarchitecture is validated via Hardware Description Language (HDL) virtual prototype simulation. The newly proposed ESPR microarchitecture is finally compared to a earlier developed reconfigurable ESPR architecture. Copyright © (2009) by the International Society for computers and Their Applications. All rights reserved.

关键词： computer hardware description languages

来源：评论

学校读者我要写书评

暂无评论

Game theory basis for control of long-lived lunar/planetary surface robots

Game theory basis for control of long-lived lunar/planetary ...

引用

作者： Huntsberger, Terry L. Sengupta, Abhijit Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena CA 91109 Advanced Robotic Controls Group NASA's Jet Propulsion Laboratory Pasadena CA Intelligent Systems Laboratory Department of Computer Science University of South Carolina SPIE ACM IEEE Computer Society INNS Advanced Concepts and Architecture Group Jet Propulsion Laboratory Pasadena CA

Current and future NASA robotic missions to planetary surfaces are tending toward longer duration and are becoming more ambitious for rough terrain access. For a higher level of autonomy in such missions, the rovers will require behavior that must also adapt to declining health and unknown environmental conditions. The MER (Mars Exploration Rovers) called Spirit and Opportunity have both passed 600 days of life on the Martian surface, with extensions to 1000 days and beyond depending on rover health. Changes in navigational planning due to degradation of the drive motors as they reach their lifetime are currently done on Earth for the Spirit rover. The upcoming 2009 MSL (Mars Science laboratory) and 2013 AFL (Astrobiology Field laboratory) missions are planned to last 300-500 days, and will possibly involve traverses on the order of multiple kilometers over challenging terrain. This paper presents a unified coherent framework called SMART (System for Mobility and Access to Rough Terrain) that uses game theoretical algorithms running onboard a planetary surface rover to safeguard rover health during rough terrain access. SMART treats rover motion, task planning, and resource management as a Two Person Zero Sum Game (TPZSG), where the rover is one player opposed by the other player called "nature" representing uncertainty in sensing and prediction of the internal and external environments. We also present preliminary results of some field studies.

关键词： Mobile robots

来源：评论

学校读者我要写书评

暂无评论

Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance 98

Effects of architectural and technological advances on the H...

引用

Proceedings of the 25th annual international symposium on computer architecture

作者： Gheith A. Abandah Edward S. Davidson Advanced Computer Architecture Laboratory University of Michigan Ann Arbor

ISBN: (纸本)9780818684913

Advances in microarchitecture, packaging, and manufacturing processes enable designers to build new systems with higher performance and scalability. Using microbenchmark techniques, we contrast the memory and communication performance of two generations of the HP/Convex Exemplar scalable parallel processing system. The SPP1000 and SPP2000 have significant architectural and implementation differences, but maintain upward binary compatibility. The SPP2000 employs manufacturing and packaging advances to obtain shorter system interconnects with wider data paths and improved functionality, thereby reducing the latency and increasing the bandwidth of remote communication. Although the memory latency is not significantly improved, newer out-of-order execution processors coupled with nonblocking caches achieve much higher memory bandwidth. The SPP2000 has a richer system interconnect topology that allows scalability to a larger number of processors. The SPP2000 also employs innovations in its coherence protocols to improve synchronization and communication performance. This paper characterizes the performance effects of these changes, and identifies some remaining inefficiencies, in the cache coherence protocol and the node configuration, that future systems should address.

关键词：

来源：评论

学校读者我要写书评

暂无评论

The edge-based design rule model revisited

引用

ACM Transactions on Design Automation of Electronic Systems 1998年第3期3卷 463-486页

作者： Riepe, Michael A. Sakallah, Karem A. University of Michigan Ann Arbor MI 48109-2122 United States Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109-2122 1301 Beal Avenue United States

A model for integrated circuit design rules based on rectangle edge constraints has been proposed by Jeppson, Christensson, and Hedenstierna. This model appears to be the most rigorous proposed to date for the description of such edge-based design rules. However, in certain rare circumstances their model is unable to express the correct design rule when the constrained edges are not adjacent in the layout. We introduce a new notation, called an edge path, which allows us to extend their model to allow for constraints between edges separated by an arbitrary number of intervening edges. Using this notation we enumerate all edge paths that are required to correctly model the original design rule macros of the JCH model, and prove that these macros are sufficient to model the most common rules. We also show how this notation allows us to directly specify many kinds of conditional design rules that required ad hoc specification under the JCH model. © 1999 ACM.

关键词： Design rule checking Design rules Layout verification Theory Verification

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：