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检索条件"机构=Advanced Computer Architecture Laboratory"

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Sponge: Portable stream programming on graphics engines

Sponge: Portable stream programming on graphics engines

引用

Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems

作者： Hormati, Amir Samadi, Mehrzad Woh, Mark Mudge, Trevor Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781450302661

Graphics processing units (GPUs) provide a low cost platform for accelerating high performance computations. The introduction of new programming languages, such as CUDA and OpenCL, makes GPU programming attractive to a wide variety of programmers. However, programming GPUs is still a cumbersome task for two primary reasons: tedious performance optimizations and lack of portability. First, optimizing an algorithm for a specific GPU is a time-consuming task that requires a thorough understanding of both the algorithm and the underlying hardware. Unoptimized CUDA programs typically only achieve a small fraction of the peak GPU performance. Second, GPU code lacks efficient portability as code written for one GPU can be inefficient when executed on another. Moving code from one GPU to another while maintaining the desired performance is a non-trivial task often requiring significant modifications to account for the hardware differences. In this work, we propose Sponge, a compilation framework for GPUs using synchronous data flow streaming languages. Sponge is capable of performing a wide variety of optimizations to generate efficient code for graphics engines. Sponge alleviates the problems associated with current GPU programming methods by providing portability across different generations of GPUs and CPUs, and a better abstraction of the hardware details, such as the memory hierarchy and threading model. Using streaming, we provide a writeonce software paradigm and rely on the compiler to automatically create optimized CUDA code for a wide variety of GPU targets. Sponge's compiler optimizations improve the performance of the baseline CUDA implementations by an average of 3.2x. Copyright © 2011 ACM.

关键词： Graphics processing unit

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Trigonometric method to handle realistic error probabilities in logic circuits

Trigonometric method to handle realistic error probabilities...

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作者： Yu, Chien-Chih Hayes, John P. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI United States

ISBN: (纸本)9783981080179

We present a novel trigonometry-based probability calculation (TPC) method for analyzing circuit behavior and reliability in the presence of errors that occur with extremely low probability. Signal and error probabilities are represented by trigonometric functions controlled by their corresponding angles. By combining trigonometric identities and Taylor expansions, the effect of an error at a particular gate is simulated as a rotation. In addition, the correlations among signals caused by reconvergence are carefully handled. The TPC method is shown to be more scalable and accurate than prior approaches, especially for very low-probability errors. We measure the performance of TPC by applying it to the ISCAS and LGSyn-91 benchmark circuits. Experimental results show that TPC achieves near-linear runtime complexity even with the largest circuits, while the accuracy gradually increases with decreasing error probabilities. © 2011 EDAA.

关键词： Timing circuits

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High-efficient architecture of Godson-T many-core processor 23

High-efficient architecture of Godson-T many-core processor

引用

23rd IEEE Hot Chips Symposium, HCS 2011

作者： Fan, Dongrui Zhang, Hao Wang, Da Ye, Xiaochun Song, Fenglong Zhang, Junchao Fan, Lingjun Advanced Micro-System Group National Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and targeted markets for AMS's Godson-T microprocessor...

ISBN: (纸本)9781467388771

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Encore: Low-cost, fine-grained transient fault recovery 44

Encore: Low-cost, fine-grained transient fault recovery

引用

44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44

作者： Feng, Shuguang Gupta, Shantanu Ansari, Amin Mahlke, Scott A. August, David I. Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States Department of Computer Science Princeton University Princeton NJ United States

ISBN: (纸本)9781450310536

To meet an insatiable consumer demand for greater performance at less power, silicon technology has scaled to unprecedented dimensions. However, the pursuit of faster processors and longer battery life has come at the cost of reliability. Given the rise of processor reliability as a first-order design constraint, there has been a growing interest in low-cost, non-intrusive techniques for transient fault detection. Many of these recent proposals have counted on the availability of hardware recovery mechanisms. Although common in aggressive out-of-order cores, hardware support for speculative rollback and recovery is less common in lower-end commodity processors. This paper presents Encore, a software-based fault recovery mechanism tailored for these lower-cost systems that lack native hardware support for speculative rollback recovery. Encore combines program analysis, profile data, and simple code transformations to create statistically idempotent code regions that can recover from faults at very little cost. Using this software-only, compiler-based approach, Encore provides the ability to recover from transient faults without specialized hardware or the costs of traditional, full-system checkpointing solutions. Experimental results show that Encore, with just 14% of runtime overhead, can safely recover, on average from 97% of transient faults when coupled with existing detection schemes. © 2011 ACM.

关键词： Fault detection

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PEPSC: A power-efficient processor for scientific computing

PEPSC: A power-efficient processor for scientific computing

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20th International Conference on Parallel architectures and Compilation Techniques, PACT 2011

作者： Dasika, Ganesh Sethia, Ankit Mudge, Trevor Mahlke, Scott ARM R and D Austin TX United States Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9780769545660

The rapid advancements in the computational capabilities of the graphics processing unit (GPU) as well as the deployment of general programming models for these devices have made the vision of a desktop supercomputer a reality. It is now possible to assemble a system that provides several TFLOPs of performance on scientific applications for the cost of a high-end laptop computer. While these devices have clearly changed the landscape of computing, there are two central problems that arise. First, GPUs are designed and optimized for graphics applications resulting in delivered performance that is far below peak for more general scientific and mathematical applications. Second, GPUs are power hungry devices that often consume 100-300 watts, which restricts the scalability of the solution and requires expensive cooling. To combat these challenges, this paper presents the PEPSC architecture - an architecture customized for the domain of data parallel scientific applications where power-efficiency is the central focus. PEPSC utilizes a combination of a two-dimensional single-instruction multiple-data (SIMD) datapath, an intelligent dynamic prefetching mechanism, and a configurable SIMD control approach to increase execution efficiency over conventional GPUs. A single PEPSC core has a peak performance of 120 GFLOPs while consuming 2W of power when executing modern scientific applications, which represents an increase in computation efficiency of more than 10X over existing GPUs. © 2011 IEEE.

关键词： Graphics processing unit

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Does low-power design imply energy efficiency for data centers? 11

Does low-power design imply energy efficiency for data cente...

引用

International Symposium on Low Power Electronics and Design (ISLPED)

作者： David Meisner Thomas F. Wenisch Advanced Computer Architecture Laboratory University of Michigan USA

ISBN: (纸本)9781612846606

Data center efficiency has quickly become a first-class design goal. In response, many studies have emerged from the academic community and industry using low-power design to help improve the energy efficiency of server hardware. Generally, these proposals hold the assumption that low-power design is inherently better for energy efficiency; this preconception stems mostly from great success in the mobile space with building low-power, energy-efficient systems. We observe that unlike mobile devices, constraining a data center server to a low power budget is arbitrary and higher power design choices can be more energy efficient. We analyze the energy efficiency design space of past commercial server designs and find that high-power servers are generally more energy efficient than low-power ones. Furthermore, we evaluate building low- or high-power server clusters and find that the small increase in the cost of cooling high-powered servers is easily outweighed by their greater efficiency.

关键词： Servers Dynamic range Cooling Correlation Sockets Atmospheric modeling Industries

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Towards a scalable data center-level evaluation methodology

Towards a scalable data center-level evaluation methodology

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IEEE International Symposium on Performance Analysis of Systems and Software

作者： David Meisner Junjie Wu Thomas F. Wenisch Advanced Computer Architecture Laboratory University of Michigan USA

As the popularity of Internet services continues to rise, the need to understand the design of the data center systems hosting these workloads becomes increasingly important. Unfortunately, research in this area has been stifled, primarily due to a lack of tools, workloads, and rigorous evaluation methodology. Traditional tools, such as architectural simulators, do not directly address data center-level issues and do not scale to simulate the thousands of machines needed for data center research. We introduce, Stochastic Queuing Simulation (SQS), our methodology for characterization and evaluation of data center systems. By leveraging techniques from stochastic modeling, queuing theory and statistical sampling, SQS uses discrete-event simulation to drive models that scale to tens of thousands of machines. Whereas detailed architectural simulations can last hours or days, SQS turnaround time is typically on the order of tens of minutes to an hour. Furthermore, computation can be distributed across cores and machines, achieving speedup using commodity clusters.

关键词： Servers Data models Computational modeling Stochastic processes Queueing analysis Instruments Analytical models

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Bundled execution of recurring traces for energy-efficient general purpose processing 44

Bundled execution of recurring traces for energy-efficient g...

引用

44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44

作者： Gupta, Shantanu Feng, Shuguang Ansari, Amin Mahlke, Scott August, David Hybrid Parallel Computing Group Intel Corporation United States Advanced Computer Architecture Laboratory University of Michigan Arbor MI United States Department of Computer Science Princeton University Princeton NJ United States

ISBN: (纸本)9781450310536

Technology scaling has delivered on its promises of increasing device density on a single chip. However, the voltage scaling trend has failed to keep up, introducing tight power constraints on manufactured parts. In such a scenario, there is a need to incorporate energy-efficient processing resources that can enable more computation within the same power budget. Energy efficiency solutions in the past have typically relied on application specific hardware and accelerators. Unfortunately, these approaches do not extend to general purpose applications due to their irregular and diverse code base. Towards this end, we propose BERET, an energy-efficient co-processor that can be configured to benefit a wide range of applications. Our approach identifies recurring instruction sequences as phases of "temporal regularity" in a program's execution, and maps suitable ones to the BERET hardware, a three-stage pipeline with a bundled execution model. This judicious off-loading of program execution to a reduced-complexity hardware demonstrates significant savings on instruction fetch, decode and register file accesses energy. On average, BERET reduces energy consumption by a factor of 3-4X for the program regions selected across a range of general-purpose and media applications. The average energy savings for the entire application run was 35% over a single-issue in-order processor. © 2011 ACM.

关键词： Energy utilization

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Highly scalable distributed dataflow analysis 11

Highly scalable distributed dataflow analysis

引用

International Symposium on Code Generation and Optimization (CGO)

作者： Joseph L. Greathouse Chelsea LeBlanc Todd Austin Valeria Bertacco Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

ISBN: (纸本)9781612843568

Dynamic dataflow analyses find software errors by tracking meta-values associated with a program's runtime data. Despite their benefits, the orders-of-magnitude slowdowns that accompany these systems limit their use to the development stage; few users would tolerate such overheads. This work extends dynamic dataflow analyses with a novel sampling system which ensures that runtime slowdowns do not exceed a user-defined threshold. While previous sampling methods are inadequate for dataflow analyses, our technique efficiently reduces the number and size of analyzed dataflows. In doing so, it allows individual users to test large, stochastically chosen sets of a process's dataflows. Large populations can therefore, in aggregate, analyze a larger portion of the program than is possible by any single user running a complete, but slow, analysis. In our experimental evaluation, we show that 1 out of every 10 users expose a number of security exploits while only experiencing a 10% performance slowdown, in contrast with the 100× overhead caused by a complete analysis that exposes the same problems.

关键词： Software Runtime Security Performance analysis Virtual machine monitors Prototypes Dynamic scheduling

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Bloom Filter Guided Transaction Scheduling

Bloom Filter Guided Transaction Scheduling

引用

IEEE Symposium on High-Performance computer architecture

作者： Geoffrey Blake Ronald G. Dreslinski Trevor Mudge Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

Contention management is an important design component to a transactional memory system. Without effective contention management to ensure forward progress, a transactional memory system can experience live-lock, which is difficult to debug in parallel programs. Early work in contention management focused on heuristic managers that reacted to conflicts between transactions by picking the most appropriate transaction to abort. Reactive methods allow conflicts to happen repeatedly as they do not try to prevent future conflicts from happening. These shortcomings of reactive contention managers have led to proposals that approach contention management as a scheduling problem - proactive managers. Proactive techniques range from throttling execution in predicted periods of high contention to preventing groups of transactions running concurrently that are predicted likely to conflict. We propose a novel transaction scheduling scheme called “Bloom Filter Guided Transaction Scheduling” (BFGTS), that uses a combination of simple hardware and Bloom filter heuristics to guide scheduling decisions and provide enhanced performance in high contention situations. We compare to two state-of-the-art transaction schedulers, “Adaptive Transaction Scheduling” and “Proactive Transaction Scheduling” and show that BFGTS attains up to a 4.6× and 1.7× improvement on high contention benchmarks respectively. Across all benchmarks it shows a 35% and 25% average performance improvement respectively.

关键词： Hardware Software Benchmark testing Data structures Registers Runtime Memory management

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