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advanced modeling of faults in Reversible circuits

Advanced modeling of faults in Reversible circuits

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East-West Design & Test Symposium (EWDTS)

作者： Ilia Polian John P. Hayes Department of Informatics and Mathematics University of Passau Passau Germany Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

This survey provides an overview of some recent developments in the testing and design validation of reversible logic circuits Reversible circuits are of interest in ultra-low-power design and in quantum information processing. We describe the fault and error models that have been proposed for these circuits and summarize their properties. We also discuss algorithms for automatic test pattern generation, design-for-testability techniques, and design debugging. We conclude by briefly examining the relationship between classical reversible circuits and quantum circuits.

关键词： Circuit faults Logic gates Integrated circuit modeling Wires Discrete Fourier transforms Automatic test pattern generation

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An ultra low power SIMD processor for wireless devices

An ultra low power SIMD processor for wireless devices

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Asilomar Conference on Signals, Systems & computers

作者： Mark Woh Sangwon Seo Chaitali Chakrabarti Scott Mahlke Trevor Mudge Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA School of Electrical Computer and Energy Engineering Arizona State University Tempe AZ USA

This paper presents an ultra low power programmable processor architecture for wireless devices that support 4G wireless communications and video decoding. To derive such an architecture, first we analyzed the kernel algorithms that constitute these applications. The characteristics of these algorithms helped define the wide-SIMD architecture, where the SIMD width can be configured at run time to the specifics of the algorithm being executed. For ultra low power operation, we advocate operating the processor at near threshold voltage. While a combination of near-threshold circuit techniques and parallel SIMD computations achieves excellent energy efficiency, near-threshold operations suffer from large delay variations due to increased process variability. The paper explores low overhead architectural techniques to tolerate and mitigate problems due to delay variations. The techniques include replication of SIMD functional units to replace faulty ones and use of an XRAM crossbar to efficiently set up the new error-free SIMD datapath.

关键词： Delay computer architecture Registers Wireless communication Decoding Algorithm design and analysis Signal processing algorithms

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Pricing of multi-energy network flow

Pricing of multi-energy network flow

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2010 IEEE International Energy Conference and Exhibition, EnergyCon 2010

作者： Schulze, Matthias Gasparovic, Goran Lee, Jieun High Voltage Laboratory Swiss Federal Institute of Technology Zurich Physikstrasse 3 8092 Zurich Switzerland Faculty of Electrical Engineering Mechanical Engineering and Naval Architecture University of Split R. Bokovia b. b. 21000 Split Croatia Dept. of Computer Science Korea Advanced Institute of Science and Technology Guseong-dong Yuseong-gu Daejeon 305-701 Korea Republic of

ISBN: (纸本)9781424493807

The network model bases upon the energy hub concept, which was developed by the Vision of Future Energy Networks (VoFEN) research group at ETH Zurich in the last years. Keynote of the concept is a combined optimization of different energy carrier. Synergetic effects are expected to give unusual optimization results, when allowing any possible energy conversion inside a specific area that constitute the hub. Costs for the energy consumption or production are generally used as the optimization criteria. Any technologies for conversion and storage are integrated in a coupling matrix, which links input and output. This paper deals with an extension to the optimization part by merging the network flows with the pricing of grid costs. The impact of network flow pricing is at first derived from theory, then translated into the energy hub concept and finally illustrated in an example. © 2010 IEEE.

关键词： Costs

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Examining OSGi from an Ideal Enterprise Software Component Model

Examining OSGi from an Ideal Enterprise Software Component M...

引用

2010 IEEE International Conference on Sofetware Engineering and Service Sciences(2010 软件工程与服务科学国际学术会议 ICSESS)

作者： Jingang Zhou Dazhe Zhao Yong Ji Jiren Liu National Engineering Research Center for Computer Software Northeastern University 110004 Shenyan National Engineering Research Center for Computer Software Northeastern University 110004 Shenyan State Key Laboratory of Advanced Software Architecture Neusoft Corporation 110179 Shenyang China National Engineering Research Center for Computer Software Northeastern University 110004 Shenyan

Component-based software development is becoming a discipline in software engineering community, but it still immature in enterprise application development. OSGi gives some insights for component-based development (CBD). By proposing an ideal component model for enterprise applications, we analyze the performance of OSGi against such a model. The result shows that OSGi is still lack of some advanced component features for CBD, although it provides a modular solution superior to plain Java. The result also contributes both to the decision making for the software developers who want to select the OSGi component technology and to the improvements to be made to OSGi.

关键词： software component component model OSGi component-based development enterprise software

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Pricing of multi-energy network flow

Pricing of multi-energy network flow

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IEEE International Energy Conference and Exhibition (EnergyCon)

作者： Matthias Schulze Goran Gašparović Jieun Lee High Voltage Laboratory Swiss Federal Institute of Technology Zurich Switzerland Faculty of Electrical Engineering and Naval Architecture Mechanical Engineering University of Split Split Croatia Department of Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea

The network model bases upon the energy hub concept, which was developed by the Vision of Future Energy Networks” (VoFEN) research group at ETH Zurich in the last years. Keynote of the concept is a combined optimization of different energy carrier. Synergetic effects are expected to give unusual optimization results, when allowing any possible energy conversion inside a specific area that constitute the hub. Costs for the energy consumption or production are generally used as the optimization criteria. Any technologies for conversion and storage are integrated in a coupling matrix, which links input and output. This paper deals with an extension to the optimization part by merging the network flows with the pricing of grid costs. The impact of network flow pricing is at first derived from theory, then translated into the energy hub concept and finally illustrated in an example.

关键词： Electricity Optimization Resistance heating Mathematical model Smart grids Equations

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CGRA express: Accelerating execution using dynamic operation fusion

CGRA express: Accelerating execution using dynamic operation...

引用

Embedded Systems Week 2009, ESWEEK 2009 - 2009 International Conference on Compilers, architecture, and Synthesis for Embedded Systems, CASES'09

作者： Park, Yongjun Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9781605586267

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalability, low cost, and energy efficiency. CGRAs have been effectively used for innermost loops that contain an abundant of instruction-level parallelism. Conversely, non-loop and outer-loop code are latency constrained and do not offer significant amounts of instruction-level parallelism. In these situations, CGRAs are ineffective as the majority of the resources remain idle. In this paper, dynamic operation fusion is introduced to enable CGRAs to effectively accelerate latency-constrained code regions. Dynamic operation fusion is enabled through the combination of a small bypass network added between function units in a conventional CGRA and a sub-cycle modulo scheduler to automatically identify opportunities for fusion. Results show that dynamic operation fusion reduced total application run-time by up to 17% on a 4x4 CGRA. Copyright 2009 ACM.

关键词： Memory architecture

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ZerehCache: Armoring cache architectures in high defect density technologies 42

ZerehCache: Armoring cache architectures in high defect dens...

引用

42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42

作者： Ansari, Amin Gupta, Shantanu Feng, Shuguang Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9781605587981

Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly sensitive to process variation due to their high density and organization. Designers typically over-provision caches with additional resources to overcome the hard-faults. However, static allocation and binding of redundant resources results in low utilization of the extra resources and ultimately limits the number of defects that can be tolerated. This work re-examines the design of process variation tolerant on-chip caches with the focus on flexibility and dynamic reconfigurability to allow a large number defects to be tolerated with modest hardware overhead. Our approach, ZerehCache, combines redundant data array elements with a permutation network for providing a higher degree of freedom on replacement. A graph coloring algorithm is used to configure the network and find the proper mapping of replacement elements. We perform an extensive design space exploration of both L1/L2 caches to identify several Pareto optimal ZerehCaches. For the yield analysis, a population of 1000 chips was studied at the 45nm technology node;L1 designs with 16% and an L2 designs with 8% area overheads achieve yields of 99% and 96%, respectively. Copyright 2009 ACM.

关键词： Pareto principle

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Bridging the Computation Gap Between Programmable Processors and Hardwired Accelerators

Bridging the Computation Gap Between Programmable Processors...

引用

15th International Symposium on High-Performance computer architecture

作者： Fan, Kevin Kudlur, Manjunath Dasika, Ganesh Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States Parakinetics Inc. NVIDIA Corporation.

ISBN: (纸本)9781424429325

New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is then able to map other loops onto the same hardware. The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor while trading off as little as 2x power and area efficiency to the non-programmable accelerator

关键词： Efficiency

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Polymorphic pipeline array: A flexible multicore accelerator with virtualized execution for mobile multimedia applications 42

Polymorphic pipeline array: A flexible multicore accelerator...

引用

42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42

作者： Park, Hyunchul Park, Yongjun Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States Texas Instruments Inc. United States

ISBN: (纸本)9781605587981

Mobile computing in the form of smart phones, netbooks, and personal digital assistants has become an integral part of our everyday lives. Moving ahead to the next generation of mobile devices, we believe that multimedia will become a more critical and product-differentiating feature. High definition audio and video as well as 3D graphics provide richer interfaces and compelling capabilities. However, these algorithms also bring different computational challenges than wireless signal processing. Multimedia algorithms are more complex featuring more control flow and variable computational requirements where execution time is not dominated by innermost vector loops. Further, data access is more complex where media applications typically operate on multi-dimensional vectors of data rather than single-dimensional vectors with simple strides. Thus, the design of current mobile platforms requires re-examination to account for these new application domains. In this work, we focus on the design of a programmable, low-power accelerator for multimedia algorithms referred to as a Polymorphic Pipeline Array, or PPA. The PPA is designed with flexibility and programmability as first-order requirements to enable the hardware to be dynamically customizable to the application. PPAs exploit pipeline parallelism found in streaming applications to create a coarse-grain hardware pipeline to execute streaming media applications. PPA resources are allocated to each stage depending on its size and ability to exploit fine-grain parallelism. Experimental results show that real-time media applications can take advantage of the static and dynamic configurability for increased power efficiency. Copyright 2009 ACM.

关键词： Smartphones

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A New Reconfigurable Network Node Processor architecture for Distributed Implementation of Ephemeral State Processing 22

A New Reconfigurable Network Node Processor Architecture for...

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22nd International Conference on Parallel and Distributed Computing and Communication Systems, PDCCS 2009

作者： Heath, J. Robert Lim, Nien Yi Calvert, Kenneth L. Griffioen, James Computer Architecture Laboratory Dept. of Electrical and Computer Engineering College of Engineering University of Kentucky LexingtonKY40506 United States Advanced Networking Laboratory Dept. of Computer Science College of Engineering University of Kentucky LexingtonKY40506 United States

ISBN: (纸本)9781615675777

Ephemeral State Processing (ESP) has been proposed as a lightweight, router-based, scalable building block supporting the construction of new and diverse end-to-end network management and other services. Each node of an ESP enhanced network would require a processor for implementation of the ESP service. An overview and background of ESP is first provided. ESP may be implemented within ESP enhanced network nodes three ways: one way is by a high performance special purpose programmable processor architecture best-fit for ESP implemented to reconfigurable Programmable Logic Device (PLD) technology. This implementation approach is addressed in this manuscript. The manuscript focus is the development, design, implementation, validation and evaluation of a most recently developed special purpose programmable Ephemeral State Processor (ESPR) microarchitecture for the implementation of ESP. Advantages of implementing ESPRs to in-field upgradeable reconfigurable platforms are addressed. A hardware prototype of the newly proposed ESPR microarchitecture is validated via Hardware Description Language (HDL) virtual prototype simulation. The newly proposed ESPR microarchitecture is finally compared to a earlier developed reconfigurable ESPR architecture. Copyright © (2009) by the International Society for computers and Their Applications. All rights reserved.

关键词： computer hardware description languages

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