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检索条件"机构=Advanced Computer Architecture Laboratory"

共 437 条记录，以下是161-170 订阅

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Adaptive online testing for efficient hard fault detection

Adaptive online testing for efficient hard fault detection

引用

IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Shantanu Gupta Amin Ansari Shuguang Feng Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

With growing semiconductor integration, the reliability of individual transistors is expected to rapidly decline in future technology generations. In such a scenario, processors would need to be equipped with fault tolerance mechanisms to tolerate in-field silicon defects. Periodic online testing is a popular technique to detect such failures; however, it tends to impose a heavy testing penalty. In this paper, we propose an adaptive online testing framework to significantly reduce the testing overhead. The proposed approach is unique in its ability to assess the hardware health and apply suitably detailed tests. Thus, a significant chunk of the testing time can be saved for the healthy components. We further extend the framework to work with the StageNet CMP fabric, which provides the flexibility to group together pipeline stages with similar health conditions, thereby reducing the overall testing burden. For a modest 2.6% sensor area overhead, the proposed scheme was able to achieve an 80% reduction in software test instructions over the lifetime of a 16-core CMP.

关键词： Fault detection Silicon System testing Hardware CMOS technology Checkpointing Pipelines Redundancy Logic Proposals

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Bridging the computation gap between programmable processors and hardwired accelerators

Bridging the computation gap between programmable processors...

引用

IEEE Symposium on High-Performance computer architecture

作者： Kevin Fan Manjunath Kudlur Ganesh Dasika Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Parakinetics Inc. Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI NVIDIA Corporation

ISBN: (纸本)9781424429325

New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper, we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is then able to map other loops onto the same hardware. The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor. The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor, while trading off as little as 2x power and area efficiency to the non-programmable accelerator.

关键词： Acceleration Hardware Application software High performance computing Application specific integrated circuits Energy efficiency Accelerator architectures Concurrent computing computer architecture Laboratories

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A dataflow-centric approach to design low power control paths in CGRAs

A dataflow-centric approach to design low power control path...

引用

Symposium on Application Specific Processors, SASP

作者： Hyunchul Park Yongjun Park Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing high computation throughput, scalability, low cost, and energy efficiency, but suffer from relatively high control path power consumption. We take the concept of a token network from dataflow machines and apply it to the control path of CGRAs to increase efficiency. As a result, instruction memory power is reduced by 74% , the overall control path power by 56%, and the total system power by 25%.

关键词： Power control Reconfigurable architectures Hardware Throughput Scalability Costs Energy efficiency Energy consumption Token networks Control systems

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On-line characterization and reconfiguration for single event upset variations

On-line characterization and reconfiguration for single even...

引用

IEEE Symposium on On-Line Testing (IOLTS)

作者： Kenneth M. Zick John P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

The amount of physical variation among electronic components on a die is increasing rapidly. There is a need for a better understanding of variations in transient fault susceptibility, and for methods of on-line adaptation to such variations. We address three key research questions in this area. First, we investigate accelerated characterization of individual latch susceptibilities. We find that on the order of 10 upsets per latch must be observed for variations to be adequately characterized. Second, we propose a method of on-line hardware reconfiguration using incremental place-and-route on FPGAs. Surprisingly, we find that highly localized place-and-route changes (e.g. restricted to groups of 8 flip-flops) are sufficient for realizing most of the possible benefits. Lastly, we quantify potential improvements in system-level soft error rates via Monte Carlo simulation experiments. The study highlights both what is required for and what can be gained by on-line adaptation.

关键词： Single event upset Hardware Field programmable gate arrays Latches Flip-flops Error analysis Threshold voltage Single event transient computer architecture Laboratories

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Power-efficient medical image processing using PUMA

Power-efficient medical image processing using PUMA

引用

Symposium on Application Specific Processors, SASP

作者： Ganesh Dasika Kevin Fan Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Graphics processing units (GPUs) are becoming an increasingly popular platform to run applications that require a high computation throughput. They are limited, however, by memory bandwidth and power and, as such, cannot always achieve their full potential. This paper presents the PUMA architecture; a domain specific accelerator designed specifically for medical imaging applications, but with sufficient generality to make it programmable. The goal is to closely match the performance achieved by GPUs in this domain but at a fraction of the power consumption. The results are quite promising; PUMA achieves up to 2X the performance of a modern GPU architecture and has up to a 54X improved efficiency on a floating point and memory intensive MRI reconstruction algorithm.

关键词： Biomedical image processing computer architecture Bandwidth Hardware Registers Parallel processing Energy consumption Graphics Acceleration Image analysis

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Using non-volatile memory to save energy in servers 09

Using non-volatile memory to save energy in servers

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： David Roberts Taeho Kgil Trevor Mudge Department of CSE Advanced Computer Architecture Laboratory University of Michigan USA Intel Corporation USA

ISBN: (纸本)9783981080155

Recent breakthroughs in circuit and process technology have enabled new usage models for non-volatile memory technologies such as flash and phase change RAM (PCRAM) in the general purpose computing environment. These technologies display high density and low power consumption as well as persistency that are appealing properties in a memory device. This paper summarizes our earlier work on improving NAND flash based disk caches and extends it to consider PCRAM. We first present the primary challenges in reliably managing non-volatile memories such as NAND flash, reviewing our past work on architectural support for flash manageability. We then provide a preliminary analysis of how our current flash manageability architecture may be simplified when we replace flash with PCRAM. Our evaluations on PCRAM shows a potential for more than a 65% throughput improvement for a disk-intensive database workload. Although more detailed studies are needed, we conclude that PCRAM is a strong contender to replace flash if it becomes cost-effective.

关键词： Nonvolatile memory Phase change random access memory Random access memory Costs Cooling computer architecture Energy consumption Throughput Circuits computer displays

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Application profiling on Cell-based clusters

Application profiling on Cell-based clusters

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Hikmet Dursun Kevin J. Barker Darren J. Kerbyson Scott Pakin Performance and Architecture Laboratory (PAL) Computer Science for HPC (CCS-1) Los Alamos National Laboratory NM USA Collaboratory for Advanced Computing and Simulations Department of Computer Science University of Southern California CA USA

In this paper, we present a methodology for profiling parallel applications executing on the IBM PowerXCell 8i (commonly referred to as the ldquoCellrdquo processor). Specifically, we examine Cell-centric MPI programs on hybrid clusters containing multiple Opteron and Cell processors per node such as those used in the petascale Roadrunner system. Our implementation incurs less than 3.2 mus of overhead per profile call while efficiently utilizing the limited local store of the Cell's SPE cores. We demonstrate the use of our profiler on a cluster of hybrid nodes running a suite of scientific applications. Our analyses of inter-SPE communication (across the entire cluster) and function call patterns provide valuable information that can be used to optimize application performance.

关键词： computer architecture Performance analysis Application software Laboratories Testing computer science Collaboration Concurrent computing Computational modeling computer simulation

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StageNetSlice: A reconfigurable microarchitecture building block for resilient CMP systems

StageNetSlice: A reconfigurable microarchitecture building b...

引用

Embedded Systems Week 2008 - 2008 International Conference on Compilers, architecture and Synthesis for Embedded Systems, CASES'08

作者： Gupta, Shantanu Feng, Shuguang Ansari, Amin Blome, Jason Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9781605584690

Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip temperatures. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Traditional techniques for dealing with device failures have relied on coarse-grained redundancy to maintain service in the face of failed components. In this work, we challenge this practice by identifying its inability to scale to high failure rate scenarios and investigate the advantages of finer-grained configurations. We use this study to motivate the design of StageNet, an embedded CMP architecture designed from its inception with reliability as a first class design constraint. StageNet relies on a reconfigurable network of replicated processor pipeline stages to maximize the useful lifetime of the chip, gracefully degrading performance toward end of life. This paper addresses the microarchitecture of the basic building block of StageNet, named StageNetSIice, which is a processor core comprised of networked pipeline stages. A naive slice design results in approximately 4X slowdown verses a traditional processor due to longer communication delays in the pipeline. However, several small design changes that eliminate inter-stage communication paths and minimize communication bandwidth reduce this overhead to 11% on average while providing high levels of fine-grain adaptability. Copyright 2008 ACM.

关键词： Integrated circuit design

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Optimus: Efficient realization of streaming applications on FPGAs

Optimus: Efficient realization of streaming applications on ...

引用

Embedded Systems Week 2008 - 2008 International Conference on Compilers, architecture and Synthesis for Embedded Systems, CASES'08

作者： Hormati, Amir Kudlur, Manjunath Mahlke, Scott Bacon, David Rabbah, Rodric Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States IBM T.J. Watson Research Center Hawthorne NY United States

ISBN: (纸本)9781605584690

In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either software or hardware implementations. The compiler uses a hierarchical compilation strategy that separates concerns between macro- and micro-functional requirements. Macro-functional concerns address how components (modules) are assembled to implement larger more complex applications. Micro-functional issues deal with synthesis issues of the module internals. Optimus thus allows software developers who lack deep hardware design expertise to transparently leverage the advantages of hardware customization without crossing the semantic gap between high level languages and hardware description languages. Optimus generates streaming hardware that achieves on average 40x speedup over our baseline embedded processor for a fraction of the energy. Additionally, our results show that streaming-specific optimizations can further improve performance by 255% and reduce the area requirements by 16% in average. These designs are competitive with Handel-C implementations for some of the same benchmarks. Copyright 2008 ACM.

关键词： Field programmable gate arrays (FPGA)

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Improving NAND Flash Based Disk Caches

Improving NAND Flash Based Disk Caches

引用

Annual International Symposium on computer architecture, ISCA

作者： Taeho Kgil David Roberts Trevor Mudge Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Flash is a widely used storage device that provides high density and low power, appealing properties for general purpose computing. Today, its usual application is in portable special purpose devices such as MP3 players. In this paper we examine its use in the server domain - a more general purpose environment. Aggressive process scaling and the use of multi-level cells continues to improve density ahead of Moorepsilas Law predictions, making flash even more attractive as a general purpose memory solution. Unfortunately, reliability limits the use of flash. To seriously consider flash in the server domain, architectural support must exist to address this concern. This paper first shows how flash can be used in todaypsilas server platforms as a disk cache. It then proposes two improvements. The first improves performance and reliability by splitting flash based disk caches into separate read and write regions. The second improves reliability by employing a programmable flash memory controller. It can change the error code strength (number of correctable bits) and the number of bits that a memory cell can store (cell density) according to the demands of the application. Our studies show that flash reduces overall power consumed by the system memory and hard disk drive up to 3 times while maintaining performance. We also show that flash lifetime can be improved by a factor of 20 when using a programmable flash memory controller, if some performance degradation (below 5%) is acceptable.

关键词： Flash memory Handheld computers computer architecture Digital audio players Split gate flash memory cells Power system reliability Error correction codes Disk drives Hardware Space exploration

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