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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China

MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.

关键词： Embedded system Payloads Switches Clocks Storage area networks Physical layer Protocols

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Hierarchical coarse-grained stream compilation for software defined radio

Hierarchical coarse-grained stream compilation for software ...

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CASES'07: 2007 International Conference on Compilers, architecture, and Synthesis for Embedded Systems

作者： Lin, Yuan Kudlur, Manjunath Mahlke, Scott Mudge, Trevor Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781595938268

Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application specific hardware. The operation throughput requirements of current third-generation (3G) wireless protocols are an order of magnitude higher than the capabilities of modern DSP processors. Due to this steep performance requirement, heterogeneous multiprocessor system-on-chip designs have been proposed to support SDR. Given the difficulty in compiling traditional digital signal processors, these new multiprocessor architectures provide even greater challenges for the programmers and compilers. In this paper, we utilize a hierarchical dataflow programming model, referred to as SPIR, that is designed for modeling SDR applications. We then present a coarse-grained data ow compilation strategy that assigns a SDR protocol's DSP kernels onto multiple processors, allocates memory buffers, and determines an execution schedule that meets a prescribed throughput. Unlike traditional approaches, coarse-grained compilation exploits task-level parallelism by scheduling concurrent DSP kernels instead of instructions. Because of the streaming nature of SDR protocols, we adapted an existing instruction-level software pipelining technique, modulo scheduling, for coarse-grained compilation. Our compilation methodology is able to generate parallel code that achieves near linear speedup on a SDR multiprocessor system. Copyright 2007 ACM.

关键词： Hierarchical systems

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Self-calibrating online wearout detection

Self-calibrating online wearout detection

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40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007

作者： Blome, Jason Feng, Shuguang Gupta, Shantanu Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)0769530478

Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology generations. Physical analysis of device failure mechanisms has shown that most wearout mechanisms projected to plague future technology generations are progressive, meaning that the circuit-level effects of wearout develop and intensify with age over the lifetime of the chip. This work leverages the progression of wearout over time in order to present a low-cost hardware structure that identifies increasing propagation delay, which is symptomatic of many forms of wearout, to accurately forecast the failure of microarchitectural structures. To motivate the use of this predictive technique, an HSPICE analysis of the effects of one particular failure mechanism, gate oxide breakdown, on gates from a standard cell library characterized for a 90 nm process is presented. This gate-level analysis is then used to demonstrate the aggregate change in output delay of high-level structures within a synthesized Verilog model of an embedded microprocessor core. Leveraging this analysis, a self-calibrating hardware structure for conducting statistical analysis of output delay is presented and its efficacy in predicting the failure of a variety of structures within the microprocessor core is evaluated. © 2007 IEEE.

关键词： Failure (mechanical)

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Effect of a Magnetic Field on the Preparation of Silver Nanowires Using Solid Electrolyte Thin Films

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Journal of Materials Science & Technology 2007年第1期23卷 39-42页

作者： Haifei YAO Jialin SUN Wei LIU Hongsan SUN Laboratory of Advanced Materials Department of Materials Science and Engineering Tsinghua University Beijing 100084 China Key Laboratory of Atomic and Molecular Nanosciences of Education Ministry and Department of Physics Tsinghua University Beijing 100084 China Computer Aided Architecture Design Laboratory Tsinghua University Beijing 100084 China

The effect of an external magnetic field on the preparation of silver nanowires was studied. The silver nanowires were synthesized using solid electrolyte RbAg4I5 thin films by applying both a direct current （DC） electric field and a magnetic field. The RbAg4I5 thin films, which were prepared by deposition at room temperature and atmospheric pressure on a NaCI substrate, were used for the transfer of Ag^＋ ions between two Ag electrodes during the preparation process. When only the DC electric field is applied, the silver ions migrate toward the cathode. On the edge of the silver film at the cathode the Ag^＋ ions congregate to form aligned nanowires. If the magnetic field is also applied perpendicular to the DC electric field, the morphology of the nanowires can be controlled by rotating the sample in the magnetic field. Experimental results show that the growth of the silver nanowires is determined by the Ag^＋ ionic flux.

关键词： Silver nanowires Solid electrolyte Magnetic field

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Enhancing design robustness with reliability-aware resynthesis and logic simulation

Enhancing design robustness with reliability-aware resynthes...

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IEEE International Conference on computer-Aided Design

作者： Smita Krishnaswamy Stephen M. Plaza Igor L. Markov John P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this problem such as TMR require high area and power overhead. In this work, soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. The key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. We describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. A key feature of these techniques is fast, on-the-fly estimation of soft error rate (SER) using our reliability evaluator AnSER. This tool is compared against prior SER evaluators and found to run orders of magnitude faster. We show empirically that our reliability-driven synthesis methods can reduce SER by 29-40% with only 5-13% area overhead.

关键词： Robustness Logic design Computational modeling Logic circuits Circuit simulation Circuit synthesis Observability CMOS logic circuits Integrated circuit reliability computer errors

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Monitoring Transient Errors in Sequential Circuits

Monitoring Transient Errors in Sequential Circuits

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Asian Test Symposium (ATS)

作者： Ramashis Das John P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Transient errors have become a major concern due to advances in technology scaling. Existing detection techniques for these errors, such as dual modular redundancy (DMR), have very high area overhead as they typically target all possible faults. In this paper, we analyze the effect of transient faults on sequential circuit behavior. We introduce the notion of transition errors (TEs) to capture the critical errors caused by both transient and permanent faults. We also present an error-monitoring scheme aimed specifically at TEs. Finally we describe experiments using the MCNC synthesis benchmark suite which show that, using the proposed monitoring scheme, all TEs can be detected with about 36% area overhead, which is significantly less than alternative approaches like DMR.

关键词： Monitoring Sequential circuits Circuit faults Electrical fault detection Single event transient Fault detection computer errors Circuit testing Logic circuits Clocks

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Extending Multicore architectures to Exploit Hybrid Parallelism in Single-thread Applications

Extending Multicore Architectures to Exploit Hybrid Parallel...

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IEEE Symposium on High-Performance computer architecture

作者： Hongtao Zhong Steven A. Lieberman Scott A. Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Chip multiprocessors with multiple simpler cores are gaining popularity because they have the potential to drive future performance gains without exacerbating the problems of power dissipation and complexity. Current chip multiprocessors increase throughput by utilizing multiple cores to perform computation in parallel. These designs provide real benefits for server-class applications that are explicitly multi-threaded. However, for desktop and other systems where single-thread applications dominate, multicore systems have yet to offer much benefit. Chip multiprocessors are most efficient at executing coarse-grain threads that have little communication. However, general-purpose applications do not provide many opportunities for identifying such threads, due to frequent use of pointers, recursive data structures, if-then-else branches, small function bodies, and loops with small trip counts. To attack this mismatch, this paper proposes a multicore architecture, referred to as Voltron that extends traditional multicore systems in two ways. First, it provides a dual-mode scalar operand network to enable efficient inter-core communication and lightweight synchronization. Second, Voltron can organize the cores for execution in either coupled or decoupled mode. In coupled mode, the cores execute multiple instruction streams in lock-step to collectively function as a wide-issue VLIW. In decoupled mode, the cores execute a set of fine-grain communicating threads extracted by the compiler. This paper describes the Voltron architecture and associated compiler support for orchestrating bi-modal execution

关键词： Multicore processing Yarn computer architecture Parallel processing Drives Performance gain Power dissipation Throughput Concurrent computing Data structures

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Self-calibrating Online Wearout Detection 40

Self-calibrating Online Wearout Detection

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Jason Blome Shuguang Feng Shantanu Gupta Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780769530475

Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology generations. Physical analysis of device failure mechanisms has shown that most wearout mechanisms projected to plague future technology generations are progressive, meaning that the circuit-level effects of wearout develop and intensify with age over the lifetime of the chip. This work leverages the progression of wearout over time in order to present a low-cost hardware structure that identifies increasing propagation delay, which is symptomatic of many forms of wearout, to accurately forecast the failure of microarchitectural structures. To motivate the use of this predictive technique, an HSPICE analysis of the effects of one particular failure mechanism, gate oxide breakdown, on gates from a standard cell library characterized for a 90 nm process is presented. This gate-level analysis is then used to demonstrate the aggregate change in output delay of high-level structures within a synthesized Verilog model of an embedded microprocessor core. Leveraging this analysis, a self- calibrating hardware structure for conducting statistical analysis of output delay is presented and its efficacy in predicting the failure of a variety of structures within the microprocessor core is evaluated.

关键词： Failure analysis Microprocessors Hardware Voltage Character generation Circuits Propagation delay Microarchitecture Electric breakdown Libraries

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Low-Cost Protection for SER Upsets and Silicon Defects

Low-Cost Protection for SER Upsets and Silicon Defects

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Design, Automation and Test in Europe Conference and Exhibition

作者： Mojtaba Mehrara Mona Attariyan Smitha Shyam Kypros Constantinides Valeria Bertacco Todd Austin Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9783981080124;3981080122

Extreme transistor scaling trends in silicon technology are soon to reach a point where manufactured systems will suffer from limited device reliability and severely reduced life-time, due to early transistor failures, gate oxide wear-out, manufacturing defects, and radiation-induced soft errors (SER). In this paper we present a low-cost technique to harden a microprocessor pipeline and caches against these reliability threats. Our approach utilizes online built-in self-test (BIST) and microarchitectural checkpointing to detect, diagnose and recover the computation impaired by silicon defects or SER events. The approach works by periodically testing the processor to determine if the system is broken. If so, we reconfigure the processor to avoid using the broken component. A similar mechanism is used to detect SER faults, with the difference that recovery is implemented by re-execution. By utilizing low-cost techniques to address defects and SER, we keep protection costs significantly lower than traditional fault-tolerance approaches while providing high levels of coverage for a wide range of faults. Using detailed gate-level simulation, we find that our approach provides 95% and 99% coverage for silicon defects and SER events, respectively, with only a 14% area overhead

关键词： Protection Silicon Transistors Manufacturing Built-in self-test Microprocessors Pipelines Microarchitecture Checkpointing Event detection

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Engineering Trust with Semantic Guardians

Engineering Trust with Semantic Guardians

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ilya Wagner Valeria Bertacco Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9783981080124

The ability to guarantee the functional correctness of digital integrated circuits and, in particular, complex microprocessors, is a key task in the production of secure and trusted systems. Unfortunately, this goal remains today an unfulfilled challenge, as even the most straightforward practical designs are released with latent bugs. Patching techniques can repair some of these escaped bugs, however, they often incur a performance overhead, and most importantly, they can only be deployed after an escaped bug has been exposed at the customer site. In this paper we present a novel approach to guaranteeing correct system operation by deploying a semantic guardian component. The semantic guardian is an additional control logic block which is included in the design, and can switch the microprocessor's mode of operation from its normal, high-performance but error-prone mode, to a secure, formally verified safe mode, guaranteeing that the execution will be functionally correct. We explore several frameworks where a selective use of the safe mode can enhance the overall functional correctness of a processor. Additionally, we observe through experimentation that semantic guardians facilitate the trade-off between the design validation effort and the performance and area cost of the final secure product. The experimental results show that the area cost and performance overheads of a semantic guardian can be as small as 3.5% and 5%, respectively

关键词： Hardware computer bugs Microprocessors Switches Costs Logic design Security Military computing computer architecture Digital integrated circuits

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