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International Design and Test Workshop

作者： Ramashis Das John P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9781424418244

We consider the impact of one-cycle transient faults on the state behavior of sequential circuits. The resultant errors are broadly classified into non-critical output errors and critical (state) transition errors. We also study the time required for recovery (self-healing) from transition errors under random input sequences, and present some experimental data for benchmark circuits.

关键词： Sequential circuits Circuit faults computer errors Transient analysis Error correction computer architecture Laboratories Clocks Integrated circuit reliability Frequency

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Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation 40

Software-Based Online Detection of Hardware Defects Mechanis...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Kypros Constantinides Onur Mutlu Todd Austin Valeria Bertacco Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Computer Architecture Group Microsoft Research Redmond WA USA

ISBN: (纸本)9780769530475

As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future processor systems, unless new online techniques become available to detect and to tolerate them while preserving the integrity of software applications running on the system. This paper proposes a new, software-based, defect detection and diagnosis technique. We introduce a novel set of instructions, called access-control extension (ACE), that can access and control the microprocessor's internal state. Special firmware periodically suspends microprocessor execution and uses the ACE instructions to run directed tests on the hardware. When a hardware defect is present, these tests can diagnose and locate it, and then activate system repair through resource reconfiguration. The software nature of our framework makes it flexible: testing techniques can be modified/upgraded in the field to trade off performance with reliability without requiring any change to the hardware. We evaluated our technique on a commercial chip-multiprocessor based on Sun's Niagara and found that it can provide very high coverage, with 99.22% of all silicon defects detected. Moreover, our results show that the average performance overhead of software-based testing is only 5.5%. Based on a detailed RTL-level implementation of our technique, we find its area overhead to be quite modest, with only a 5.8% increase in total chip area.

关键词： Hardware Silicon Circuit testing computer architecture Software testing Electronics industry Fault detection Checkpointing System recovery Degradation

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Design and Analysis of LDPC Decoders for Software Defined Radio

Design and Analysis of LDPC Decoders for Software Defined Ra...

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IEEE Workshop on Signal Processing Systems (SIPS)

作者： Sangwon Seo Trevor Mudge Yuming Zhu Chaitali Chakrabarti Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA Arizona State University USA

Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.

关键词： Parity check codes Software radio Throughput Iterative decoding computer architecture Code standards Bipartite graph Assembly Wireless application protocol Pipelines

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Data Access Partitioning for Fine-grain Parallelism on Multicore architectures 40

Data Access Partitioning for Fine-grain Parallelism on Multi...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Michael Chu Rajiv Ravindran Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Advanced Computer Architecture Laboratory Ann Arbor MI Parallel Computing Platforms group Microsoft Corporation Ann Arbor MI Java Compilers and Tools Laboratory at Hewlett-Packard Ann Arbor MI

ISBN: (纸本)9780769530475

The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a single chip requires programmer and compiler intervention to increase the amount of parallel work possible. Much of the recent work has fallen into the areas of coarse-grain parallelization: new programming models and different ways to exploit threads and data-level parallelism. This work focuses on a complementary direction, improving performance through automated fine-grain parallelization. The main difficulty in achieving a performance benefit from fine-grain parallelism is the distribution of data memory accesses across the data caches of each core. Poor choices in the placement of data accesses can lead to increased memory stalls and low resource utilization. We propose a profile-guided method for partitioning memory accesses across distributed data caches. First, a profile determines affinity relationships between memory accesses and working set characteristics of individual memory operations in the program. Next, a program-level partitioning of the memory operations is performed to divide the memory accesses across the data caches. As a result, the data accesses are proactively dispersed to reduce memory stalls and improve computation parallelization. A final detailed partitioning of the computation instructions is performed with knowledge of the cache location of their associated data. Overall, our data partitioning reduces stall cycles by up to 51 % versus data-incognizant partitioning, and has an overall speedup average of 30% over a single core processor.

关键词： Multicore processing Parallel processing Programming profession Program processors Multiprocessor interconnection networks computer architecture Parallel programming Yarn Microarchitecture Laboratories

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Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping

Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dyn...

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IEEE Symposium on High-Performance computer architecture

作者： Nathan Clark Amir Hormati Sami Yehia Scott Mahlke Krisztian Flautner Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA ARM Limited Cambridge UK

Microprocessor designers commonly utilize SIMD accelerators and their associated instruction set extensions to provide substantial performance gains at a relatively low cost for media applications. One of the most difficult problems with using SIMD accelerators is forward migration to newer generations. With larger hardware budgets and more demands for performance, SIMD accelerators evolve with both larger data widths and increased functionality with each new generation. However, this causes difficult problems in terms of binary compatibility, software migration costs, and expensive redesign of the instruction set architecture. In this work, we propose Liquid SIMD to decouple the instruction set architecture from the SIMD accelerator. SIMD instructions are expressed using a processor's baseline scalar instruction set, and light-weight dynamic translation maps the representation onto a broad family of SIMD accelerators. Liquid SIMD effectively bypasses the problems inherent to instruction set modification and binary compatibility across accelerator generations. We provide a detailed description of changes to a compilation framework and processor pipeline needed to support this abstraction. Additionally, we show that the hardware overhead of dynamic optimization is modest, hardware changes do not affect cycle time of the processor, and the performance impact of abstracting the SIMD accelerator is negligible. We conclude that using dynamic techniques to map instructions onto SIMD accelerators is an effective way to improve computation efficiency, without the overhead associated with modifying the instruction set

关键词： Hardware computer architecture Application software Instruction sets Delay Costs Microprocessors Performance gain Acceleration computer aided instruction

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Effective low-power scan architecture-PowerCut

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第3期44卷 473-478页

作者： Wang, Wei Han, Yinhe Hu, Yu Li, Xiaowei Zhang, Yousheng School of Computer and Information Hefei University of Technology Hefei 230009 China Advanced Test Technology Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China

It is obvious that scan testing is the prevalent design for testability (DFT) in very large scale integrated circuits test. However, scan architecture in digital circuits causes much power consumption because when scan vectors are loaded into a scan chain, the effect of scan-ripple propagates to the combinational logic and redundant switching occurs in the combinational gates during the entire vectors shifting period. Hence, low-power design becomes a challenge for scan test. In this paper, a low-power scan architecture-PowerCut is proposed for minimizing power consumption during scan test, which is based on scan chain modification techniques. Blocking logic using transmission gates is inserted into the scan chain to reduce the dynamic power in shift cycle. At the same time, based on minimum leakage vector, a controlling unit is inserted. It makes the circuit slip into low leakage state during shift cycle. Thus, leakage power is also decreased. Experiments results indicate that this architecture can effectually reduce the power during scan test, and it has little improvement in area or delay overhead, compared with other low cost existing methods.

关键词： Integrated circuit testing

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Checking equivalence of quantum circuits and states

Checking equivalence of quantum circuits and states

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IEEE International Conference on computer-Aided Design

作者： George F. Viamontes Igor L. Markov John P. Hayes Lockheed Martin ATL Cherry Hill NJ USA Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Among the post-CMOS technologies currently under investigation, quantum computing (QC) holds a special place. QC offers not only extremely small size and low power, but also exponential speed-ups for important simulation and optimization problems. It also poses new CAD problems that are similar to. but more challenging, than the related problems in classical (non-quantum) CAD. such as determining if two states or circuits are functionally equivalent. While differences in classical states are easy to detect, quantum states, which are represented by complex-valued vectors, exhibit subtle differences leading to several notions of equivalence. This provides flexibility in optimizing quantum circuits, but leads to difficult new equivalence-checking issues for simulation and synthesis. We identify several different equivalence-checking problems and present algorithms for practical benchmarks, including quantum communication and search circuits, which are shown to be very fast and robust for hundreds of qubits.

关键词： Quantum computing Circuit synthesis Circuit simulation Computational modeling computer architecture Logic circuits Phase measurement Flexible printed circuits Robustness Protection

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Fault tolerant communication algorithm for network on chip

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2007年第4期19卷 508-514页

作者： Zhang, Lei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China Advanced Test Technology Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

This paper proposes a random routing algorithm with end-to-end feedback. Random routing has the capability of handling random transmission errors efficiently with high forwarding speed. End-to-end feedback promises the correctness of transmission and reduces the power consumption. Experimental results demonstrated that our random routing algorithm has lower latency, lower power consumption, and can provide on-chip communication with high reliability.

关键词： Error correcting and detecting Fault tolerant Flooding algorithm Network on chip Random routing Random walk Reliability

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Modulo graph embedding: Mapping applications onto coarse-grained reconfigurable architectures

Modulo graph embedding: Mapping applications onto coarse-gra...

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CASES 2006: International Conference on Compilers, architecture and Synthesis for Embedded Systems

作者： Park, Hyunchul Fan, Kevin Kudlur, Manjunath Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595935436

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost and energy efficiency. CGRAs consist of an array of function units and register files generally organized as a two dimensional grid. The most difficult challenge with deploying CGRAs is compiler scheduling technology that can map software implementations of compute intensive loops onto the array. Traditional schedulers are not suitable because they do not take into account the explicit routing of operand values that is necessary. In essence, the problem of binding operations to time slots and resources is extended to also include explicit routing of operands from producers to consumers. To tackle this problem, this paper introduces a software pipelining technique for mapping loop bodies onto CGRAs, referred to as modulo graph embedding. We leverage graph embedding from graph theory, which is used to draw graphs onto a target space. The loop body is essentially drawn onto the CGRA mesh, subject to modulo resource usage constraints. Modulo graph embedding is effective because it can take into account the communication structure of the loop body during mapping. On average, a compute utilization of 56-68% is achieved for a set of loop kernels across three 4x4 CGRA designs. Copyright 2006 ACM.

关键词： Embedded systems

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Streamroller: Automatic synthesis of prescribed throughput accelerator pipelines

Streamroller: Automatic synthesis of prescribed throughput a...

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CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Kudlur, Manjunath Fan, Kevin Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements. © Copyright 2006 ACM.

关键词： Pipeline processing systems

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