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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

引用

CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Fan, Kevin Kudlur, Manjunath Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable. © Copyright 2006 ACM.

关键词： computer hardware

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FlashCache: A NAND flash memory file cache for low power web servers

FlashCache: A NAND flash memory file cache for low power web...

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CASES 2006: International Conference on Compilers, architecture and Synthesis for Embedded Systems

作者： Kgil, Taeho Mudge, Trevor Advanced Computer Architecture Laboratory University of Michigan Ann Arbor United States

ISBN: (纸本)1595935436

We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a relatively small DRAM, which includes a primary file buffer cache, and a flash memory secondary file buffer cache. Compared to a conventional DRAM-only architecture, our architecture consumes orders of magnitude less idle power while remaining cost effective. This is a result of using flash memory, which consumes orders of magnitude less idle power than DRAM and is twice as dense. The client request behavior in web servers, allows us to show that the primary drawbacks of flash memory?endurance and long write latencies?can easily be overcome. In fact the wear-level aware management techniques that we propose are not heavily used. Copyright 2006 ACM.

关键词： Flash memory

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Game theory basis for control of long-lived lunar/planetary surface robots

Game theory basis for control of long-lived lunar/planetary ...

引用

作者： Huntsberger, Terry L. Sengupta, Abhijit Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena CA 91109 Advanced Robotic Controls Group NASA's Jet Propulsion Laboratory Pasadena CA Intelligent Systems Laboratory Department of Computer Science University of South Carolina SPIE ACM IEEE Computer Society INNS Advanced Concepts and Architecture Group Jet Propulsion Laboratory Pasadena CA

Current and future NASA robotic missions to planetary surfaces are tending toward longer duration and are becoming more ambitious for rough terrain access. For a higher level of autonomy in such missions, the rovers will require behavior that must also adapt to declining health and unknown environmental conditions. The MER (Mars Exploration Rovers) called Spirit and Opportunity have both passed 600 days of life on the Martian surface, with extensions to 1000 days and beyond depending on rover health. Changes in navigational planning due to degradation of the drive motors as they reach their lifetime are currently done on Earth for the Spirit rover. The upcoming 2009 MSL (Mars Science laboratory) and 2013 AFL (Astrobiology Field laboratory) missions are planned to last 300-500 days, and will possibly involve traverses on the order of multiple kilometers over challenging terrain. This paper presents a unified coherent framework called SMART (System for Mobility and Access to Rough Terrain) that uses game theoretical algorithms running onboard a planetary surface rover to safeguard rover health during rough terrain access. SMART treats rover motion, task planning, and resource management as a Two Person Zero Sum Game (TPZSG), where the rover is one player opposed by the other player called "nature" representing uncertainty in sensing and prediction of the internal and external environments. We also present preliminary results of some field studies.

关键词： Mobile robots

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Parallelizing post-placement timing optimization 20

Parallelizing post-placement timing optimization

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20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006

作者： Kim, Jiyoun Papaefthymiou, Marios C. Neves, Jose L. Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States IBM Server Group 2455 South Road Poughkeepsie NY 12533 United States

ISBN: (纸本)1424400546

This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations into a task graph, our novel modeling scheme provides an efficient representation of the timing and spatial relations among timing optimization tasks. Our new partitioning algorithm then assigns the task graph into multiple sessions of parallel processes, so that interprocessor communication is completely eliminated during each session. This partitioning scheme is especially useful for parallelizing processes with heavily connected tasks and, therefore, high communication requirements. For circuits with 20-130 thousand cells, the partitioning heuristic achieves speedups in excess of 5× without degrading solution quality by dynamically utilizing 1-8 processors. © 2006 IEEE.

关键词： Time domain analysis

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On-Chip Test Generation Using Linear Subspaces

On-Chip Test Generation Using Linear Subspaces

引用

IEEE European Test Symposium (ETS)

作者： R. Das I.L. Markov J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses linear algebraic concepts to partition the vector space of tests into subspaces (clusters). A subspace is defined by a compact set of basis vectors. We give an algorithm to compute sets of basis vectors defining the clusters. We also describe a low-cost logic circuit based on Gray codes that reproduces the subspaces from these basis vectors. Experimental results are presented which show that this approach reduces on-chip hardware overhead and test application time, while also guaranteeing full fault coverage

关键词： Vectors Automatic testing Circuit faults Circuit testing Built-in self-test Fault detection Clustering algorithms Partitioning algorithms Logic circuits Reflective binary codes

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Compiler-directed data partitioning for muiticluster processors

Compiler-directed data partitioning for muiticluster process...

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International Symposium on Code Generation and Optimization (CGO)

作者： M.L. Chu S.A. Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Multicluster architectures overcome the scaling problem of centralized resources by distributing the datapath, register file, and memory subsystem across multiple clusters connected by a communication network. Traditional compiler partitioning algorithms focus solely on distributing operations across the clusters to maximize instruction-level parallelism. The distribution of data objects is generally ignored. In this work, we examine explicit partitioning of data objects and its affects on operation partitioning. The partitioning of data objects must consider several factors: object size, access frequency/pattern, and dependence patterns between operations that manipulate the objects. This work proposes a compiler-directed approach to synergistically partition both data objects and computation across multiple clusters. First, a global view of the application determines the interaction between data memory objects and their associated computation. Next, data objects are partitioned across multiple clusters with knowledge of the associated computation required by the application. Finally, the resulting distribution of the data objects is relayed to a region-level computation partitioner, which carefully places computation operations in a performance-centric manner.

关键词： Registers Delay computer architecture Wire Clustering algorithms Partitioning algorithms Parallel processing Distributed computing Costs Bandwidth

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Streamroller:: automatic synthesis of prescribed throughput accelerator pipelines

Streamroller:: automatic synthesis of prescribed throughput ...

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International Conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Scott Mahlke Kevin Fan Manjunath Kudlur Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements.

关键词： Throughput Pipelines Hardware Kernel Design methodology Cost function Linear accelerators High level synthesis Algorithm design and analysis Embedded computing

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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

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International Conference on Hardware/Software Codesign and System Synthesis (CODES)

作者： Scott Mahlke Manjunath Kudlur Hyunchul Park Kevin Fan Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

关键词： Hardware Acceleration Costs Algorithm design and analysis Application software Decoding Energy efficiency Accelerator architectures computer architecture Laboratories

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Distance-Guided Hybrid Verification with GUIDO 06

Distance-Guided Hybrid Verification with GUIDO

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： S. Shyam V. Bertacco Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9783981080100

Constrained random simulation is a widespread technique used to perform functional verification on complex digital designs, because it can generate simulation vectors at a very high rate. However, the generation of high-coverage tests remains a major challenge even in light of this high performance. In this paper we present Guido, a hybrid verification software that uses formal verification techniques to guide the simulation towards a verification goal. Guido is novel in that 1) it guides the simulation by means of a distance function derived from the circuit structure, and 2) it has a trace sequence controller that monitors and controls the direction of the simulation by striking a balance between random chance and controlled hill-climbing. We present experimental results indicating that Guido can tackle complex designs, including a picoJava microprocessor, and reach a verification goal in far fewer simulation cycles than random

关键词： Cost function Circuit simulation Computational modeling computer simulation Testing Formal verification Scalability computer architecture Microprocessors Design engineering

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Veri cation Through the Principle of Least Astonishment

Veri cation Through the Principle of Least Astonishment

引用

IEEE International Conference on computer-Aided Design

作者： Beth Isaksen Valeria Bertacco Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Assessing the correctness of a digital design is a challenging task hampered by extremely large circuit netlists, counterintuitive property descriptions and ill-defined specifications. In this paper we propose a new verification methodology, inspired by the principle of least astonishment. The underlying idea is to provide an automatic assessment of what constitutes "common behavior" for a system, and use this to detect any anomaly in the design. Deviant behavior is presented to the verification engineer through intuitive, compact diagrams which lend themselves to quick inspection for correctness. To enable this methodology we introduce Inferno, a new tool which can analyze the results of a logic simulation trace and automatically extract high-level diagrams representing the design's transaction activity across any user-defined interface. In addition, Inferno can automatically generate a checker module corresponding to a given transaction, suitable for use in a wide range of verification methodologies. We envision the deployment of Inferno in a closed-loop constraint-random simulation methodology where any new transaction detected on the interface is presented to the user for analysis and, once deemed legal, it is merged into an "approved transactions" checker, which flags the detection of any new type of transactions. We provide a series of examples and experimental results to show the effectiveness of Inferno and some of its possible uses

关键词： Design engineering Signal design Inspection Analytical models Hardware computer bugs Permission Formal verification Error correction computer architecture

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