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检索条件"机构=Advanced Computer Architecture Laboratory"

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Shielding against design flaws with field repairable control logic

Shielding against design flaws with field repairable control...

引用

Design Automation Conference

作者： I. Wagner V. Bertacco T. Austin Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs that escape into silicon will only grow in the future. In this paper, we propose a novel hardware patching mechanism that can detect design errors which escaped the verification process, and can correct them directly in the field. We accomplish this goal through a simple field-programmable state matcher, which can identify erroneous configurations in the processor's control state and switch the processor into formally-verified degraded performance mode, once a "match" occurs. When the instructions exposing the design flaw are committed, the processor is switched back to normal mode. We show that our approach can detect and correct infrequently-occurring errors with almost no performance impact and has approximately 2% area overhead

关键词： Logic design Error correction computer bugs Hardware Degradation Formal verification Switches Pipelines computer architecture Computational modeling

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PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor

PicoServer: Using 3D stacking technology to enable a compact...

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作者： Kgil, Taeho D'Souza, Shaun Saidi, Ali Binkert, Nathan Dreslinski, Ronald Mudge, Trevor Reinhardt, Steven Flautner, Krisztian Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor ARM Ltd. 110 Fullbourn Road Cambridge United Kingdom Hewlett-Packard Labs. Reservoir Labs Inc.

ISBN: (纸本)1595934510

In this paper, we show how 3D stacking technology can be used to implement a simple, low-power, high-performance chip multiprocessor suitable for throughput processing. Our proposed architecture, PicoServer, employs 3D technology to bond one die containing several simple slow processing cores to multiple DRAM dies sufficient for a primary memory. The 3D technology also enables wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency in turn reduces power and means that thermal constraints, a concern with 3D stacking, are easily *** PicoServer architecture specifically targets Tier 1 server applications, which exhibit a high degree of thread level parallelism. An architecture targeted to efficient throughput is ideal for this application domain. We find for a similar logic die area, a 12 CPU system with 3D stacking and no L2 cache outperforms an 8 CPU system with a large on-chip L2 cache by about 14% while consuming 55% less power. In addition, we show that a PicoServer performs comparably to a Pentium 4-like class machine while consuming only about 1/10 of the power, even when conservative assumptions are made about the power consumption of the PicoServer. Copyright © 2006 ACM.

关键词： Three dimensional computer graphics

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900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Progr...

引用

Custom Integrated Circuits Conference (CICC)

作者： Juang-ying Chueh Visvesh Sathe Marios C. Papaefthymiou Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann Arbor MI USA

A resonant clock network with programmable driver and loading is designed in a 0.13mum CMOS technology. The 2mm times 2mm distribution network has on-chip inductors and performs a forced oscillation at the rate of a reference clock programmable in the 900MHz to 1.2GHz range. Clock amplitude and energy efficiency trade-offs at and off resonance are explored with various driver configurations. Energy efficiency per cycle is 1.39 to 1.56 times greater than previous resonant distribution networks

关键词： Resonance Clocks Switches Detectors Driver circuits CMOS technology Network-on-a-chip Inductors Energy efficiency Frequency

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A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks

A Lightweight Scheme for Trust Relationship Establishment in...

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International Conference on computer and Information Technology (CIT)

作者： Lei Xie Yongjun Xu Xiaowei Li Yuefei Zhu Institute of Information Engineering Information and Engineering University Zhengzhou China Advanced Test Technology Laboratory Key Laboratory of Computer System and Architecture Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Ubiquitous sensor networks are application oriented system, which are composed of a large number of cooperative sensor nodes. The identification of individual sensor node is important especially for some security-sensitive applications. In this paper, we focus on the establishment of trust relationship among wireless sensor nodes, and try to combine the message authentication and identity authentication as a countermeasure to hostile attack. Accompanied with a simple lightweight key pre-distribution algorithm, in which each node sends only one message, we propose a lightweight trust relationship establishing scheme for ubiquitous sensor networks. The new scheme, which works without a trusted authority in the network, is not only concise in format but effective in practice to ensure network trusted and secure.

关键词： Authentication Protocols Pervasive computing Wireless sensor networks Information security Sensor systems and applications computer networks Ubiquitous computing Base stations Laboratories

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Design and Implementation of Turbo Decoders for Software Defined Radio

Design and Implementation of Turbo Decoders for Software Def...

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IEEE Workshop on Signal Processing Systems (SIPS)

作者： Yuan Lin Scott Mahlke Trevor Mudge Chaitali Chakrabarti Alastair Reid Krisztian Flautner Advanced Computer Architecture Laboratory University of Michigan at Ann Arbor Ann Arbor USA Advanced Computer Architecture Laboratory University of Michigan at Ann Arbor Department of Electrical Engineering Arizona State University USA ARM Ltd. Cambridge United Kingdom

Software defined radio (SDR) is an emerging paradigm for wireless terminals, in which the physical layer of communication protocols is implemented in software rather than by ASICs. Many of the current and next generation wireless protocols include turbo coding because of its superior performance. However, turbo decoding is computationally intensive, and its low power implementations have typically been in ASICs. This paper presents a case study of algorithm-architecture co-design of turbo decoder for SDR. We present a programmable DSP architecture for SDR that includes a set of architectural features to accelerate turbo decoder computations. We then present a parallel window scheduling for MAX-Log-MAP component decoder that matches well with the DSP architecture. Finally, we present a software implementation of turbo decoder for W-CDMA on the DSP architecture and show that it achieves 2 Mbps decoding throughput

关键词： Decoding Software radio Digital signal processing computer architecture Wireless application protocol Physical layer Turbo codes Acceleration Processor scheduling Multiaccess communication

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NXG05-4: Fast Packet Classification using Group Bit Vector

NXG05-4: Fast Packet Classification using Group Bit Vector

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IEEE Globecom 2006

作者： Tong Liu Huawei Li Xiaowei Li Yinhe Han Advanced Test Technology Laboratory Key Laboratory of Computer System anChinesed Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Packet classification is important in fulfilling the requirements of new services such as policy-based routing in next generation networks. In this paper, we propose a novel bit vector based two-dimensional packet classification algorithm called Group Bit Vector. The key feature of the proposed algorithm is its ability to set the length of the bit vector to perform AND operation (the operation bit vector) regardless of the size of rule databases by effectively aggregating the rules and constructing particular groups of a limited number of members. Moreover, the proposed algorithm avoids the problem of false matches, which may be brought by rules aggregation. Thus, the length of the operation bit vector can be adjusted to be suitable to the width of memories to improve the performance. Experimental results demonstrate the flexibility and effectiveness of the proposed algorithm.

关键词： Classification algorithms Databases Hardware Routing Next generation networking Protocols System testing computer architecture Electronic mail Performance analysis

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Parallelizing post-placement timing optimization 06

Parallelizing post-placement timing optimization

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jiyoun Kim M.C. Papaefthymiou J.L. Neves Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA IBM Server Group Poughkeepsie NY USA

ISBN: (纸本)9781424400546

This paper presents an efficient modeling scheme and a partitioning heuristic for parallelizing VLSI post-placement timing optimization. Encoding the paths with timing violations into a task graph, our novel modeling scheme provides an efficient representation of the timing and spatial relations among timing optimization tasks. Our new partitioning algorithm then assigns the task graph into multiple sessions of parallel processes, so that interprocessor communication is completely eliminated during each session. This partitioning scheme is especially useful for parallelizing processes with heavily connected tasks and, therefore, high communication requirements. For circuits with 20-130 thousand cells, the partitioning heuristic achieves speedups in excess of 5times without degrading solution quality by dynamically utilizing 1-8 processors

关键词： Timing Design optimization Very large scale integration Degradation Delay Partitioning algorithms Circuits Parallel processing Design automation computer architecture

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BulletProof: a defect-tolerant CMP switch architecture

BulletProof: a defect-tolerant CMP switch architecture

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IEEE Symposium on High-Performance computer architecture

作者： K. Constantinides S. Plaza J. Blome B. Zhang V. Bertacco S. Mahlke T. Austin M. Orshansky Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transient errors, and transistor wear-out. Unless these challenges are addressed, computer vendors can expect low yields and short mean-times-to-failure. In this paper, we examine the challenges of designing complex computing systems in the presence of transient and permanent faults. We select one small aspect of a typical chip multiprocessor (CMP) system to study in detail, a single CMP router switch. To start, we develop a unified model of faults, based on the time-tested bathtub curve. Using this convenient abstraction, we analyze the reliability versus area tradeoff across a wide spectrum of CMP switch designs, ranging from unprotected designs to fully protected designs with online repair and recovery capabilities. Protection is considered at multiple levels from the entire system down through arbitrary partitions of the design. To better understand the impact of these faults, we evaluate our CMP switch designs using circuit-level timing on detailed physical layouts. Our experimental results are quite illuminating. We find that designs are attainable that can tolerate a larger number of defects with less overhead than naive triple-modular redundancy, using domain-specific techniques such as end-to-end error detection, resource sparing, automatic circuit decomposition, and iterative diagnosis and reconfiguration.

关键词： Switches Circuit faults Protection computer architecture Silicon Nanoscale devices computer errors Switching circuits Timing Redundancy

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Constraint-driven floorplan repair

Constraint-driven floorplan repair

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Design Automation Conference

作者： M.D. Moffitt A.N. Ng I.L. Markov M.E. Pollack Artificial Intelligence Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Floorplanning algorithms have traditionally underperformed experienced designers, even when relatively simple interconnect metrics are concerned. However, the sheer scale of modern systems on chip makes an all-manual design flow infeasible. In this paper, we propose a new efficient automated approach to the floorplan repair problem, where a set of violated design constraints are satisfied by applying small changes to an existing rough floorplan. Such a floor-plan can be produced by a human designer, by a scalable placement algorithm, or result from engineering adjustments to a pre-existing floorplan. In all cases, overlapping modules must be separated, and in some instances, modules may need to be repositioned to satisfy other requirements. The algorithmic framework we propose is built upon an expressive graph-based encoding of constraints. While capable of representing floorplans with or without overlapping modules, it can also support the outline of the core area, fixed module locations, region constraints, proximity and alignment constraints, etc. Instead of applying randomized local search in the hope of satisfying these constraints, we track all implications of imposed constraints and resolve violations by invoking gradual modifications to the floor-plan. The primary focus of this paper is on a particularly efficient conflict-directed algorithm for floorplan repair and legalization. It is shown to completely eliminate overlaps from layouts produced by Capo 9.4, Feng Shui 5.1 and APlace 2.01 on IBM-HB benchmarks with hard blocks; typically requiring negligible runtime and increasing interconnect length by only several percent. Furthermore, we are able to generate legal solutions for these instances that surpass previously reported results in wirelength by an average of roughly 7%

关键词： Algorithm design and analysis Laboratories Artificial intelligence computer architecture Modems Constraint optimization Design optimization Humans Shape Encoding

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A Tamper-resistance Key Pre-distribution Scheme for Wireless Sensor Networks

A Tamper-resistance Key Pre-distribution Scheme for Wireless...

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International Conference on Grid and Cooperative Computing Workshops (GCCW)

作者： Lei Xie Hongsong Zhu Yongjun Xu Yuefei Zhu Institute of Information Engineering Information and Engineering University Zhengzhou China Advanced Test Technology Laboratory Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Wireless sensor network (WSN), which is integrated with many technologies such as sensor, embedded computing, wireless communication and distributed information processing etc., is becoming an important branch of ubiquitous computing research. WSN is composed of a large number of distributed sensor nodes, so to ensure the sensor nodes dependable is essential to security of whole network. By introducing a lightweight tamper-resistance design based on security co-processor into sensor nodes, this paper loosens up the security assumptions of WSN, and redefines the objectives of WSN security. Based on such secure infrastructure, the paper also proposes a concise and effective key pre-distribution scheme, in which each node needs to send only one cluster key announcement message and cluster key net can be set up within neighborhood

关键词： Wireless sensor networks Pervasive computing Ubiquitous computing Information security computer networks computer architecture Sensor arrays Design engineering Laboratories Embedded computing

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