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Probabilistic predicate-aware modulo scheduling 04

Probabilistic predicate-aware modulo scheduling

引用

International Symposium on Code Generation and Optimization (CGO)

作者： M. Smelyanskiy S. Mahlke E.S. Davidson Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780769521022

Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transformation is that the compiler must unconditionally assign resources to predicated operations. However, a resource is only put to productive use when the predicate associated with an operation evaluates to True. To reduce this superfluous commitment of resources, we propose probabilistic predicate-aware scheduling to assign multiple operations to the same resource at the same time, thereby over-subscribing its use. Assignment is performed in a probabilistic manner using a combination of predicate profile information and predicate analysis aimed at maximizing the benefits of over-subscription in view of the expected degree of conflict. Conflicts occur when two or more operations assigned to the same resource have their predicates evaluate to True. A predicate-aware VLIW processor pipeline detects such conflicts, recovers, and correctly executes the conflicting operations. By increasing the effective throughput of a fixed set of resources, probabilistic predicate-aware scheduling provided an average of 20% performance gain in our evaluations on a 4-issue processor, and 8% gain on a 6-issue processor.

关键词： Processor scheduling Pipelines Runtime VLIW Performance gain computer architecture Laboratories Information analysis Performance analysis Throughput

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Gate sizing and V/sub t/ assignment for active-mode leakage power reduction

Gate sizing and V/sub t/ assignment for active-mode leakage ...

引用

IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Feng Gao J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduce leakage power. We assume a standard-cell-based design flow where the available cell sizes and threshold voltages (V/sub t/'s) are given, and model the optimization as a mixed-integer linear programming (MLP) problem. In addition to the exact model, two faster approximate MLP models are proposed, along with CAD tools that generate the models automatically. We present experimental results which show that optimal designs derived from the exact MLP model can achieve the same performance as all-low-V/sub t/ unit-size designs, but with only one third the leakage power. The approximate MLP models can be solved about 25 times faster than the optimal model with negligible errors. All the proposed models can be extended to take dynamic power and multiple supply voltages into consideration.

关键词： Threshold voltage Energy consumption Delay Leakage current Linear programming Dynamic voltage scaling Design optimization Design automation Power supplies Circuits

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High-performance QuIDD-based simulation of quantum circuits 04

High-performance QuIDD-based simulation of quantum circuits

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： G.F. Viamontes I.L. Markov J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780769520858

Simulating quantum computation on a classical computer is a difficult problem. The matrices representing quantum gates, and vectors modeling qubit states grow exponentially with the number of qubits. It has been shown experimentally that the QuIDD (Quantum Information Decision Diagram) datastructure greatly facilitates simulations using memory and runtime that are polynomial in the number of qubits. In this paper, we present a complexity analysis which formally describes this class of matrices and vectors. We also present an improved implementation of QuIDDs which can simulate Grover's algorithm for quantum search with the asymptotic runtime complexity of an ideal quantum computer up to negligible overhead.

关键词： Circuit simulation Quantum computing Computational modeling Runtime Quantum mechanics computer simulation Tensile stress computer architecture Laboratories Polynomials

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Discovering 1-FT routes in mobile ad hoc networks

Discovering 1-FT routes in mobile ad hoc networks

引用

International Conference on Dependable Systems and Networks (DSN)

作者： R. Venkatasubramanian J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Transmitting messages in mobile wireless networks typically involves on-demand route discovery implemented via network-wide broadcast. Due to the dynamic nature of the network topology the life-time of a route is very short, so a source frequently requires a new route to an old destination. Simultaneous discovery of multiple routes can reduce the overhead due to repeated route discovery broadcasts. Previously proposed multipath protocols do not guarantee discovery of alternative paths if they exist. We propose a multiple route discovery algorithm (ALTDSR) that finds a (multihop) primary path between a source and a destination, and a set of alternative paths. We introduce dominator relationships between primary and non-primary path nodes. Using dominators, we characterize alternative paths that bypass an intermediate node on the primary path. We develop algorithms that guarantee finding a set of alternative paths to tolerate any single node fault on the primary path, if such a set of alternative paths exists. We present simulation results which show that under high mobility conditions, ALTDSR delivers substantially more packets (around 75% more) than dynamic source routing (DSR) with moderate increase in routing overhead.

关键词： Intelligent networks Mobile ad hoc networks

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FLASH: foresighted latency-aware scheduling heuristic for processors with customized datapaths 04

FLASH: foresighted latency-aware scheduling heuristic for pr...

引用

International Symposium on Code Generation and Optimization (CGO)

作者： Manjunath Kudlur K. Fan M. Chu Rajiv Ravindran N. Clark S. Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780769521022

Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing the hardware to suit an application. A central problem is creating compilers that are capable of dealing with the heterogeneous and nonuniform hardware created by the customization process. The processor datapath provides an effective area to customize, but specialized datapaths often have nonuniform connectivity between the function units, making the effective latency of a function unit dependent on the consuming operation. Traditional instruction schedulers break down in this environment due to their locally greedy nature of binding the best choice for a single operation even though that choice may be poor due to a lack of communication paths. To effectively schedule with nonuniform connectivity, we propose a foresighted latency-aware scheduling heuristic (FLASH) that performs lookahead across future scheduling steps to estimate the effects of a potential binding. FLASH combines a set of lookahead heuristics to achieve effective foresight with low compile-time overhead.

关键词： Processor scheduling Application specific processors Costs Hardware Registers Delay computer architecture Pipelines Laboratories Application software

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Automatic synthesis of customized local memories for multicluster application accelerators

Automatic synthesis of customized local memories for multicl...

引用

International Conference on Application Specific Systems (ASAP), architectures and Processors

作者： M. Kudlur K. Fan M. Chu S. Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Distributed local memories, or scratchpads, have been shown to effectively reduce cost and power consumption of application-specific accelerators while maintaining performance. The design of the local memory organization must take several factors into account, including the memory bandwidth and size requirements of the program and the distribution of program data among the memories. In addition, when register structures and function units in the accelerator are clustered, the effects of intercluster communication should be taken into account. This work proposes a technique to synthesize the local memory architecture of a clustered accelerator using a phase-ordered approach. First, the dataflow graph is pre-partitioned to define a performance-centric grouping of the operations. Second, memory synthesis is performed by combining multiple data structures into a set of physical memories that minimizes cost while maintaining a performance threshold. Finally, post-partitioning is performed to determine the final assignment of operations to clusters given the memory organization. Results show that customization reduces memory cost from 2% to 59% over a naive scheme that utilizes one physical memory per program data structure. Further, pre-partitioning is shown to reduce the intercluster communication required to achieve a fixed performance.

关键词： Acceleration Application software Costs Bandwidth Delay Data structures computer architecture Laboratories Energy consumption Registers

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Fixed-load energy recovery memory for low power

Fixed-load energy recovery memory for low power

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IEEE computer Society Annual Symposium on VLSI

作者： Joohee Kim C.H. Ziesler Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

This paper proposes an energy recovery SRAM that achieves significant dynamic power savings by recovering energy stored in large bit line capacitors. Memory load to power-clock during write is kept fixed by precharging non-selective after each write cycle. Load during read is also kept fixed by not driving the bit lines with power-clock for read. A simple power-clock generator control scheme that exploits the fixed-load characteristics of the energy recovery memory is introduced to achieve substantially reduced total system power dissipation. The power-clock control scheme reduces system dissipation by preventing the replenishing operation of the power-clock generator while not writing and thus does not require energy transfer between the memory and the power-clock. Hspice simulations of a full custom 128/spl times/256 energy recovery SRAM core show over 4.77/spl times/ more efficient write operations in comparison with its conventional counterpart at 2.5V, 250MHz. Simulations with a power-clock generator show that disabling power-clock replenishing, whenever memory does not write, achieves savings over 1.47/spl times/ on total system power over that of a system without the power-clock control.

关键词： Power generation Random access memory Capacitors Power dissipation Control systems Timing Writing Energy efficiency Driver circuits Computational modeling

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Empirical evaluation of timing and power in resonant clock distribution

Empirical evaluation of timing and power in resonant clock d...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Juang-Ying Chueh C.H. Ziesler M.C. Papaefthymiou Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann Arbor MI USA

Resonant clocking is an attractive alternative to conventional clock distribution due to its significant potential for reducing clocking power. Typically, resonant clock systems rely on sinusoidal clock signals to synchronize flip-flops. Understanding clock skew and power is particularly important in these systems, because unlike their conventional counterparts, resonant clock networks do not use any buffers. We have performed a simulation study of clock skew and power in resonant H-shape clock distribution networks with sinusoidal waveforms. Focusing on the impact of width, spacing, and loading on clock skew, our study suggests practical design guidelines for low-skew resonant clocking. Our results show that compared to conventional clocking, properly designed resonant clocking yields comparable or better skew. Furthermore, simultaneous improvements in skew and power of resonant clock are possible through width scaling. Our experiments also confirm the theoretical prediction that energy dissipation in resonant clock networks scales with RC/T, where RC is the load of the network, and T is the clock period.

关键词： Timing Resonance Clocks Capacitance Flip-flops Frequency Voltage Energy consumption Power generation Power dissipation

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Experimental evaluation of resonant clock distribution

Experimental evaluation of resonant clock distribution

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IEEE computer Society Annual Symposium on VLSI

作者： Juang-ying Chueh C.H. Ziesler M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Energy recovery (a.k.a. adiabatic) systems present an attractive alternative to conventional designs due to their significant potential for reducing power. In practical versions of these systems, flip-flops are typically synchronized by a sinusoidal power-clock waveform through a resonant clock distribution network. Understanding clock skew is particularly important in energy recovery systems, because unlike their conventional counterparts, they do not use square clock waveforms or buffers. We have performed an experimental evaluation of clock skew in resonant H-shape clock distribution networks with sinusoidal waveforms. Our results show that compared to conventional clock distribution methodologies in high performance processors, properly designed low-power resonant clocking provides comparable or better skew. Our paper is the first study to suggest a number of practical design guidelines for low-skew resonant clocking, through a systematic investigation of the impact of width, spacing, and loading of the clock tree on clock skew.

关键词： Resonance Clocks Switches Capacitance Frequency Voltage Flip-flops RLC circuits Power generation Very large scale integration

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Constant-load energy recovery memory for efficient high-speed operation

Constant-load energy recovery memory for efficient high-spee...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Joohee Kim M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

This paper proposes a constant-load SRAM design for highly efficient recovery of bit-line energy with a resonant power-clock supply. For each bit-line pair, the proposed SRAM includes a dummy bit-line of sufficient capacitance to ensure that the memory array presents a constant capacitive load to the power-clock, regardless of data or operation. Using a single-phase power-clock waveform, read and write operations are performed with single-cycle latency. The efficiency of the proposed SRAM has been assessed through simulations of 128/spl times/256 arrays with 0.25 /spl mu/m process parameters and a 42/58 write/non-write access pattern. Assuming lossless power-clock generation, the proposed SRAM dissipates 37% less power than its conventional counterpart at 400 MHz/2.5 V. When the overhead of power-clock generation is included, the proposed SRAM dissipates at least 27% less power than conventional SRAM.

关键词： Random access memory Capacitance Resonance Delay Clocks Power generation Circuits Recycling Frequency Permission

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