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Constant-load energy recovery memory for efficient high-speed operation

Constant-load energy recovery memory for efficient high-spee...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Joohee Kim M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

This paper proposes a constant-load SRAM design for highly efficient recovery of bit-line energy with a resonant power-clock supply. For each bit-line pair, the proposed SRAM includes a dummy bit-line of sufficient capacitance to ensure that the memory array presents a constant capacitive load to the power-clock, regardless of data or operation. Using a single-phase power-clock waveform, read and write operations are performed with single-cycle latency. The efficiency of the proposed SRAM has been assessed through simulations of 128/spl times/256 arrays with 0.25 /spl mu/m process parameters and a 42/58 write/non-write access pattern. Assuming lossless power-clock generation, the proposed SRAM dissipates 37% less power than its conventional counterpart at 400 MHz/2.5 V. When the overhead of power-clock generation is included, the proposed SRAM dissipates at least 27% less power than conventional SRAM.

关键词： Random access memory Capacitance Resonance Delay Clocks Power generation Circuits Recycling Frequency Permission

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Testing for missing-gate faults in reversible circuits

Testing for missing-gate faults in reversible circuits

引用

Asian Test Symposium (ATS)

作者： J.P. Hayes I. Polian B. Becker Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Albert Ludwig University Freiburg im Breisgau Germany

Logical reversibility occurs in low-power applications and is an essential feature of quantum circuits. Of special interest are reversible circuits constructed from a class of reversible elements called k-CNOT (controllable NOT) gates. We review the characteristics of k-CNOT circuits and observe that traditional fault models like the stuck-at model may not accurately represent their faulty behavior or test requirements. A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies. It is shown that MGFs are highly testable, and that all MGFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. A design-for-test (DFT) method to make an arbitrary circuit fully testable for MGFs using a single test vector is described. Finally, we present simulation results to determine (near) optimal test sets and DFT configurations for some benchmark circuits.

关键词： Circuit testing Circuit faults Quantum computing Design for testability Electrical fault detection Fault detection computer architecture Laboratories Application software Circuit simulation

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Microarchitectural power modeling techniques for deep sub-micron microprocessors

Microarchitectural power modeling techniques for deep sub-mi...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Nam Sung Kim T. Kgil V. Bertacco T. Austin T. Mudge Microprocessor Research INTEL Research Laboratory Hillsboro OR USA Advanced Computer Architecture Lab University of Michigan Ann Arbor MI USA

The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance has moved to the fore. To satisfy this demand several microarchitectural power simulators have been developed around SimpleScalar, a widely used microarchitectural performance simulator They have proven to be very useful at providing insights into power/performance trade-offs. However, they are neither parameterized nor technology scalable. In this paper, we propose more accurate parameterized power modeling techniques reflecting the actual technology parameters as well as input switching-events for memory and execution units. Compared to HSPICE, the proposed techniques show 93% and 91% accuracies for those blocks, but with a much faster simulation time. We also propose a more realistic power modeling technique for external I/O. In general, our approach includes more detailed microarchitectural and circuit modeling than has been the case in earlier simulators, without incurring a significant simulation time overhead - it can be as small as a few percent.

关键词： Microarchitecture Microprocessors Table lookup Circuit simulation Integrated circuit modeling Energy consumption Batteries Permission Power dissipation computer architecture

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An algorithm for geometric load balancing with two constraints

An algorithm for geometric load balancing with two constrain...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： J. Kim M. Papaefthymiou A. Tayyab Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann Arbor MI USA IBM Microelectronics Austin TX USA

Summary form only given. We describe an algorithm for partitioning 2-weighted geometric graphs, so that each of the two weights is evenly distributed among all partitions and cutsize is minimal. This algorithm is applicable to load balancing problems in parallel computing, including scientific computation or circuit optimization, in which computational load depends on multiple factors, and geometric proximity needs to be preserved. We first show that for two continuous weight distributions, there always exists an L-shape separator that divides the two weights exactly. Based on this fact, we then give a practical and efficient heuristic for 2/sup p/-way partitioning. Our heuristic relies on recursive bipartitioning and runs in O(nlgn+m2/sup p/) time, where n is the number of vertices and m is the number of rows in the graph. In experiments with geometric graphs obtained from placed benchmark VLSI circuits, our heuristic generates balanced partitions with imbalance no greater than 2%, very short runtimes, and good cutsizes. For example, given a geometric graph with n>100,000, our heuristic computes a 32-way partitioning with 0.46% maximum imbalance within 0.5 second.

关键词： Load management Parallel processing Partitioning algorithms Concurrent computing Particle separators Very large scale integration Circuits computer architecture Laboratories Microelectronics

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Cache scrubbing in microprocessors: myth or necessity?

Cache scrubbing in microprocessors: myth or necessity?

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Pacific Rim International Symposium on Dependable Computing

作者： S.S. Mukherjee J. Emer T. Fossum S.K. Reinhardt Massachusetts Microprocessor Design Center Intel Corporation Shrewsbury MA USA Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann Arbor MI USA

Transient faults from neutron and alpha particle strikes in large SRAM caches have become a major problem for microprocessor designers. To protect these caches, designers often use error correcting codes (ECC), which typically provide single-bit error correction and double-bit error detection (SECDED). Unfortunately, two separate strikes could still flip two different bits in the same ECC-protected word. This we call a temporal double-bit error. SECDED ECC can only detect, not correct such errors. We show how to compute the mean time to failure for temporal double-bit errors. Additionally, we show how fixed-interval scrubbing - in which error checkers periodically access cache blocks and remove single-bit errors - can mitigate such errors in processor caches. Our analysis using current soft error rates shows that only very large caches (e.g., hundreds of megabytes to gigabytes) need scrubbing to reduce the temporal double-bit error rate to a tolerable range.

关键词： Microprocessors Error correction codes Error correction Hardware computer architecture Protection Writing Bandwidth Error analysis Multiprocessing systems

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Techniques to reduce the soft error rate of a high-performance microprocessor

Techniques to reduce the soft error rate of a high-performan...

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Annual International Symposium on computer architecture, ISCA

作者： C. Weaver J. Emer S.S. Mukherjee S.K. Reinhardt Massachusetts Microprocessor Design Center Intel Corporation Ann Arbor MI USA Massachusetts Microprocessor Design Center Intel Corporation Hudson MA USA EECS Department Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Transient faults due to neutron and alpha particle strikes pose a significant obstacle to increasing processor transistor counts in future technologies. Although fault rates of individual transistors may not rise significantly, incorporating more transistors into a device makes that device more likely to encounter a fault. Hence, maintaining processor error rates at acceptable levels will require increasing design effort. This paper proposes two simple approaches to reduce error rates and evaluates their application to a microprocessor instruction queue. The first technique reduces the time instructions sit in vulnerable storage structures by selectively squashing instructions when long delays are encountered. A fault is less likely to cause an error if the structure it affects does not contain valid instructions. We introduce a new metric, MITF (Mean Instructions To Failure), to capture the trade-off between performance and reliability introduced by this approach. The second technique addresses false detected errors. In the absence of a fault detection mechanism, such errors would not have affected the final outcome of a program. For example, a fault affecting the result of a dynamically dead instruction would not change the final program output, but could still be flagged by the hardware as an error. To avoid signalling such false errors, we modify a pipeline's error detection logic to mark affected instructions and data as possibly incorrect rather than immediately signaling an error. Then, we signal an error only if we determine later that the possibly incorrect value could have affected the program's output.

关键词： Error analysis Microprocessors Circuit faults computer errors Error correction computer architecture Protection Delay Performance loss Hardware

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The impact of resource partitioning on SMT processors 03

The impact of resource partitioning on SMT processors

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： S.E. Raasch S.K. Reinhardt Advanced Computer Architecture Laboratory EECS Department University of Michigan USA

ISBN: (纸本)9780769520216

Simultaneous multithreading (SMT) increases processor throughput by multiplexing resources among several threads. Despite the commercial availability of SMT processors, several aspects of this resource sharing are not well understood. For example, academic SMT studies typically assume that resources are shared dynamically, while industrial designs tend to divide resources statically among threads. This study seeks to quantify the performance impact of resource partitioning policies in SMT machines, focusing on the execution portion of the pipeline. We find that for storage resources, such as the instruction queue and reorder buffer, statically allocating an equal portion to each thread provides good performance, in part by avoiding starvation. The enforced fairness provided by this partitioning obviates sophisticated fetch policies to a large extent. SMT's potential ability to allocate storage resources dynamically across threads does not appear to be of significant benefit. In contrast, static division of issue bandwidth has a negative impact on throughput. SMT's ability to multiplex bursty execution streams dynamically onto shared function units contributes to its overall throughput. Finally, we apply these insights to SMT support in clustered architectures. Assigning threads to separate clusters eliminates intercluster communication; however, in some circumstances, the resulting partitioning of issue bandwidth cancels out the performance benefit of eliminating communication.

关键词： Surface-mount technology Yarn Pipelines Bandwidth Interleaved codes Buffer storage Resource management Process design computer architecture Laboratories

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Processor acceleration through automated instruction set customization 36

Processor acceleration through automated instruction set cus...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： N. Clark Hongtao Zhong S. Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780769520438

Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded applications. Hardware, in the form of new function units (or co-processors), and the corresponding instructions, are added to a baseline processor to meet the critical computational demands of a target application. The central challenge with this approach is the large degree of human effort required to identify and create the custom hardware units, as well as porting the application to the extended processor. In this paper, we present the design of a system to automate the instruction set customization process. A dataflow graph design space exploration engine efficiently identifies profitable computation subgraphs from which to create custom hardware, without artificially constraining their size or shape. The system also contains a compiler subgraph matching framework that identifies opportunities to exploit and generalize the hardware to support more computation graphs. We demonstrate the effectiveness of this system across a range of application domains and study the applicability of the custom hardware across the domain.

关键词： Acceleration Hardware Embedded computing Power demand Coprocessors computer aided instruction Humans Space exploration Engines Shape

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Gate-level simulation of quantum circuits 03

Gate-level simulation of quantum circuits

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Asia and South Pacific Design Automation Conference

作者： G.F. Viamontes M. Rajagopalan I.L. Markov J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780780376601

Simulating quantum computation on a classical computer is a difficult problem. The matrices representing quantum gates, and vectors modeling qubit states grow exponentially with an increase in the number of qubits. However, by using a new data structure called the Quantum Information Decision Diagram (QuIDD) that exploits the structure of quantum operators, many of these matrices and vectors can be represented in a form that grows polynomially. Using QuIDDs, we implemented a general-purpose quantum computing simulator in C++ called QuIDDPro and tested it on Grover's algorithm. Our QuIDD technique asymptotically outperforms other known simulation techniques.

关键词： Circuit simulation Quantum computing Computational modeling computer simulation Vectors Physics computing Tensile stress Quantum mechanics computer errors computer architecture

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Tutorial: basic concepts in quantum circuits 03

Tutorial: basic concepts in quantum circuits

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Design Automation Conference

作者： J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9781581136883

Summary form only given. Over the last decade a new way to compute has been defined which, unlike conventional methods, is based on quantum mechanics rather than classical physics. This fundamental change in paradigm can, in principle, solve some important and hitherto intractable problems such as prime factorization of large numbers. This tutorial presentation reviews the basics of quantum computation and the design of circuits to implement quantum algorithms. The starting point is the notion of a quantum bit or qubit. Because of the superposition property of quantum states, n qubits can store 2/sup n/ numbers simultaneously, implying a type of massive parallelism. Furthermore, quantum states allow powerful forms of interaction such as entanglement that have no classical counterparts. Qubits are fragile, however, and are altered by measurement; hence quantum circuits must follow very different rules from classical ones. The differences between quantum and classical logic circuits is discussed and illustrated. Finally, the physical implementation of quantum devices is considered, along with the prospects for practical quantum computers.

关键词： Tutorial Quantum computing Physics computing computer architecture Quantum mechanics Algorithm design and analysis Parallel processing Quantum entanglement Logic circuits

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