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检索条件"机构=Advanced Computer Architecture Laboratory"

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Razor: a low-power pipeline based on circuit-level timing speculation 36

Razor: a low-power pipeline based on circuit-level timing sp...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： D. Ernst Nam Sung Kim S. Das S. Pant R. Rao Toan Pham C. Ziesler D. Blaauw T. Austin K. Flautner T. Mudge Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA ARM Limited Cambridge UK

ISBN: (纸本)9780769520438

With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities is very rare. In this paper, we propose a new approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability-tolerant comparator then validates latch values sampled with the fast clock. In the event of timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor pipeline was designed in a 0.18 /spl mu/m technology and was analyzed. Razor energy overhead during normal operation is limited to 3.1%. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%).

关键词： Pipelines Timing Clocks Dynamic voltage scaling Voltage control Error correction Tuned circuits Delay Frequency Silicon

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Development of computer programme for the description of plastic deformation by slip 7

Development of computer programme for the description of pla...

引用

7th Korea-Russia International Symposium on Science and Technology, KORUS 2003

作者： Semenov, M.E. Kolupaeva, S.N. Laboratory of Computer Aided Design of Advanced Materials Institute of Strength Physics and Materials Science Akademichesky pr. 2/1 Tomsk634021 Russia Department of Applied Mathematics Tomsk State University of Architecture and Building Solyanaya sq. 2 Tomsk634003 Russia

ISBN: (纸本)8978686184

The interface and structure of a package of applied programs for the description of plastic deformation by slip in f.c.c. materials are developed. The mathematical model used for calculations is based on the set of differential equations of balance of deformation defects in f.c.c. materials. The processes of generation and annihilation of deformation defects have essentially different rates, and the system of ODE (ordinary differential equations) is stiff. Application of implicit absolutely steady methods is necessary in this situation, because classical Runge-Kutta's methods can require much time for calculations. In this case the use of implicit multistep Gear's method of the variable order for decision the system of ODE is more effective. The applied programs for the description of plastic deformation are oriented for the users who have different qualification in programming and are not require an experience of decision of ODE. © 2003 7th Korea-Russia Intl Sym on Science.

关键词： Ordinary differential equations

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Predicate-aware scheduling: a technique for reducing resource constraints

Predicate-aware scheduling: a technique for reducing resourc...

引用

International Symposium on Code Generation and Optimization (CGO)

作者： M. Smelyanskiy S.A. Mahlke E.S. Davidson H.-H.S. Lee Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Georgia Institute of Technology School of ECE Atlanta GA USA

Predicated execution enables the removal of branches wherein segments of branching code are converted into straight-line segments of conditional operations. An important, but generally ignored side effect of this transformation is that the compiler must assign distinct resources to all the predicated operations at a given time to ensure that those resources are available at run-time. However, a resource is only put to productive use when the predicates associated with its operations evaluate to True. We propose predicate-aware scheduling to reduce the superfluous commitment of resources to operations whose predicates evaluate to False at run-time. The central idea is to assign multiple operations to the same resource at the same time, thereby oversubscribing its use. This assignment is intelligently performed to ensure that no two operations simultaneously assigned to the same resource will have both of their predicates evaluate to True. Thus, no resource is dynamically oversubscribed. The overall effect of predicate aware scheduling is to use resources more efficiently, thereby increasing performance when resource constraints are a bottleneck.

关键词： Processor scheduling Runtime VLIW Resource management computer architecture Laboratories Performance evaluation Pipeline processing Parallel processing Registers

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Low-cost on-line fault detection using control flow assertions

Low-cost on-line fault detection using control flow assertio...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Rajesh Venkatasubramanian J.P. Hayes B.T. Murray Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Brighton Technical Center Delphi Automotive Systems Brighton MI UK

A control flow fault occurs when a processor fetches and executes an incorrect next instruction. Executable assertions, i.e., special instructions that check some invariant properties of a program, provide a powerful and low-cost method for on-line detection of hardware-induced control flow faults. We propose a technique called ACFC (Assertions for Control Flow Checking) that assigns an execution parity to a basic block, and uses the parity bit to detect faults. Using a graph model of a program, we classify control flow faults into skip, re-execute and multi-path faults. We derive some necessary conditions for these faults to manifest themselves as execution parity errors. To force a control flow fault to excite a parity error, the target program is instrumented with additional instructions. Special assertions are inserted to detect such parity errors. We have a developed a preprocessor that takes a C program as input and inserts ACFC assertions automatically. We have implemented a software-based fault injection tool SFIG which takes advantage of the GNU debugger. Fault injection experiments show that ACFC incurs less performance overhead (around 47%) and memory overhead (around 30%) than previous techniques, with no significant loss in fault coverage.

关键词： Fault detection computer architecture Laboratories Automotive engineering Rivers Testing Costs Registers Instruments Performance loss

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Effective support of simulation in computer architecture instruction

Effective support of simulation in computer architecture ins...

引用

2002 Workshop on computer architecture Education, WCAE 2002

作者： Weaver, Christopher T. Larson, Eric Austin, Todd Advanced Computer Architecture Laboratory University of Michigan United States

ISBN: (纸本)9781450347310

The use of simulation is well established in academic and industry research as a means of evaluating architecture trade-offs. The large code base, complex architectural models, and numerous configurations of these simulators can consternate those just learning computer architecture. Even those experienced with computer architecture, may have trouble adapting a simulator to their needs, due to the code complexity and simulation method. In this paper we present tools we have developed to make simulation more accessible in the classroom by aiding the process of launching simulations, interpreting results and developing new architectural models.

关键词： computer architecture

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Energy recovering static memory

Energy recovering static memory

引用

International Symposium on Low Power Electronics and Design (ISLPED)

作者： Joohee Kim C.H. Ziesler M.C. Papaefthymiou Advanced Computer Architecture Laboratory Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

This paper proposes an energy-recovering (a.k.a. adiabatic) static RAM with a novel driver that reduces power dissipation by efficiently recovering energy from the bit/word line capacitors. Powered by a single-phase sinusoidal power-clock, our SRAM delivers read and write operations with single-cycle latency. To that end, a precharge-low scheme is employed along with a modified sense amplifier design that achieves high efficiency at differential voltages near V/sub SS/. A simple control circuit is used to maintain driver operation in synchrony with the power-clock waveform. Feedback circuitry from the driver output to the control circuit ensures that out driver remains efficient, independent of the access pattern. Our energy recovering SRAM functions correctly while achieving substantial energy savings over a wide range of supply voltages and operating frequencies. Hspice simulations of a simple full-custom adiabatic 256/spl times/256 SRAM, that includes the energy recovering bit/word line drivers, the cell array, and the sense amplifiers, show over 2.6x energy savings at 3V, 300MHz in comparison with its conventional counterpart.

关键词： Driver circuits Random access memory Voltage Feedback circuits Read-write memory Power dissipation Capacitors Delay Differential amplifiers Frequency synchronization

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On-line monitor design of finite-state machines

On-line monitor design of finite-state machines

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IEEE International On-Line Testing Workshop

作者： Feng Gao J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

On-line monitoring is a useful technique for ensuring system reliability. By continuously supervising the system's operation, a wide range of problems, such as physical defects, transient faults and design errors, can be detected A monitor M*'s behavior can be viewed as an abstraction of the target system M's behavior, and can be represented by a homomorphic mapping from M to M*. We present a systematic procedure to select homomorphisms and measure their costs. Experimental results are also presented which quantify some basic trade-offs between area overhead and fault coverage.

关键词： Condition monitoring Testing Conferences

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Efficient dynamic scheduling through tag elimination

Efficient dynamic scheduling through tag elimination

引用

Annual International Symposium on computer architecture, ISCA

作者： D. Ernst T. Austin Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory arrays accessed during instruction wake-up. The performance of the scheduler can be improved by decreasing the number of tag comparisons necessary to schedule instructions. Using detailed simulation-based analyses, we find that most instructions enter the window with at least one of their input operands already available. By putting these instructions into specialized windows with fewer tag comparators, load capacitance on the scheduler critical path can be reduced, with only very small effects on program throughput. For instructions with multiple unavailable operands, we introduce a last-tag speculation mechanism that eliminates all remaining tag comparators except those for the last arriving input operand. By combining these two tag-reduction schemes, we are able to construct dynamic schedulers with approximately one quarter of the tag comparators found in conventional designs. Conservative circuit-level timing analyses indicate that the optimized designs are 20-45% faster and require 10-20% less power depending on instruction window size.

关键词： Dynamic scheduling Technical Activities Guide -TAG Pipelines Resource management Logic Registers Processor scheduling computer architecture computer aided instruction Costs

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Drowsy caches: simple techniques for reducing leakage power

Drowsy caches: simple techniques for reducing leakage power

引用

Annual International Symposium on computer architecture, ISCA

作者： K. Flautner Nam Sung Kim S. Martin D. Blaauw T. Mudge ARM Ltd Cambridge UK Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA The University of Michigan Advanced Computer Architecture Lab Ann Arbor MI

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink the dominant component of this power loss will be leakage. However, during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving, low-power drowsy mode. Moving lines into and out of drowsy state incurs a slight performance loss. In this paper we investigate policies and circuit techniques for implementing drowsy caches. We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. According to our projections, in a 0.07 um CMOS process, drowsy caches will be able to reduce the total energy (static and dynamic) consumed in the caches by 50%-75%. We also argue that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.

关键词： Dynamic voltage scaling Voltage control Energy consumption computer architecture Circuit simulation Threshold voltage Leakage current Inverters Semiconductor device modeling Predictive models

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A statistical model of input glitch propagation and its application in power macromodeling

A statistical model of input glitch propagation and its appl...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Xun Liu M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Power macromodeling technique can result in huge underestimation without the consideration of input glitches. In this paper, we propose a statistical model for the propagation of input glitches and their effects on circuit power consumption. Based on this model, we develop an analytical power macromodeling approach incorporating input glitches. Specifically, we divide the macromodel parameter space into three regions and characterize each region separately. We have evaluated the proposed technique on ISCAS85 and LGSynth93 benchmark circuits. Compared with switch level simulation results, the average power estimation errors are 1.8% and 3.1% for combinational and sequential circuits, respectively. Our model also provides useful insight for glitchy circuit identification and input glitch power reduction.

关键词： Statistics Table lookup Phase estimation Power dissipation Switches Switching circuits Sequential circuits Signal generators Registers Interpolation

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