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Human systems integration and advanced technology in engineering department workload and manpower reduction

NAVAL ENGINEERS JOURNAL 2003年第1期115卷 57-65页

作者： Lively, KA Seman, AJ Kirkpatrick, M KENNETH A. LIVELY graduated from the University of Colorado with a BS in applied mathematics and an MS in mathematics in 1976 and from the Massachusetts Institute of Technology with an MS in electrical engineering and the degree ocean engineer in naval architecture and marine engineering in 1984. He retired from the U.S. Navy in 1989 after 23 years of service. Assignments included electrical officer on the USS Constellation (CV 64) project engineer for the DDG 51 machinery control system (NAVSEA) and DDG 51 Technical Director (NAVSEA). He was vice president of the PDI Division of Bird-Johnson Company from July 1989 to November 1998 where he managed various gas turbine and machinery controls related development projects. He joined Anteon Corporation's Systems Engineering Group as senior controls engineer in December 1998 where he provided technical support to the integrated power systems program (NAVSEA PMS 510) and managed the Office of Naval Research Afloat Laboratory. DR. MARK KIRKPATRICK is currently an independent consultant in human factors and work-load/manning analysis and modeling. He holds a Ph.D. degree in experimental psychology from The Ohio State University and has 34 years of experience in applied human factors. From 1982 through 2000 Dr. Kirkpatrick served as the senior vice president of Carlow International. Prior to joining Carlow in 1982 Dr. Kirkpatrick served as a member of the technical staff at North American Rockwell's Missiles Division and as a project director and vice president for Essex Corporation. His areas of expertise include workload simulation task analysis operator-in-the-loop simulation human performance experimentation statistical analysis and human factors T&E. He has directed and/or participated in human factors projects for the U.S. Navy U.S. Army NASA Department of Transportation the U.S. Nuclear Regulatory Commission and private industry. ANTHONY J. SEMAN III is the technical manager for the reduced ship's crew by virtual presence (RSVP) advanced technology d

Aboard current ships, such as the DDG 51, engineering control and damage control activities are manpower intensive. It is anticipated that, for future combatants, the workload demand arising from operation of systems under conditions of normal steaming and during casualty response will need to be markedly reduced via automated monitoring, autonomous control, and other technology initiatives. Current DDG 51 class ships can be considered as a manpower baseline and under Condition III typical engineering control involves seven to eight watchstanders at manned stations in the Central Control Station, the engine rooms and other machinery spaces. In contrast to this manning level, initiatives such as DD 21 and the integrated engineering plant (IEP) envision a partnership between the operator and the automation system, with more and more of the operator's functions being shifted to the automation system as manning levels decrease. This paper describes some human systems integration studies of workload demand reduction and, consequently, manning reduction that can be achieved due to application of several advanced technology concepts. advanced system concept studies in relation to workload demand are described and reviewed including. Piecemeal applications of diverse automation and remote control technology concepts to selected high driver tasks in current DDG 51 activities. Development of the reduced ship's crew by virtual presence system that will provide automated monitoring and display to operators of machinery health, compartment conditions, and personnel health. The IEP envisions the machinery control system as a provider of resources that are used by various consumers around the ship. Resource needs and consumer priorities are at all times dependent upon the ship's current mission and the availability of equipment pawnbrokers.

关键词： Naval warfare

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On-line monitor design of finite-state machines

On-line monitor design of finite-state machines

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IEEE International On-Line Testing Workshop

作者： Feng Gao J.P. Hayes Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

On-line monitoring is a useful technique for ensuring system reliability. By continuously supervising the system's operation, a wide range of problems, such as physical defects, transient faults and design errors, can be detected A monitor M*'s behavior can be viewed as an abstraction of the target system M's behavior, and can be represented by a homomorphic mapping from M to M*. We present a systematic procedure to select homomorphisms and measure their costs. Experimental results are also presented which quantify some basic trade-offs between area overhead and fault coverage.

关键词： Condition monitoring Testing Conferences

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Efficient dynamic scheduling through tag elimination

Efficient dynamic scheduling through tag elimination

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Annual International Symposium on computer architecture, ISCA

作者： D. Ernst T. Austin Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory arrays accessed during instruction wake-up. The performance of the scheduler can be improved by decreasing the number of tag comparisons necessary to schedule instructions. Using detailed simulation-based analyses, we find that most instructions enter the window with at least one of their input operands already available. By putting these instructions into specialized windows with fewer tag comparators, load capacitance on the scheduler critical path can be reduced, with only very small effects on program throughput. For instructions with multiple unavailable operands, we introduce a last-tag speculation mechanism that eliminates all remaining tag comparators except those for the last arriving input operand. By combining these two tag-reduction schemes, we are able to construct dynamic schedulers with approximately one quarter of the tag comparators found in conventional designs. Conservative circuit-level timing analyses indicate that the optimized designs are 20-45% faster and require 10-20% less power depending on instruction window size.

关键词： Dynamic scheduling Technical Activities Guide -TAG Pipelines Resource management Logic Registers Processor scheduling computer architecture computer aided instruction Costs

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Drowsy caches: simple techniques for reducing leakage power

Drowsy caches: simple techniques for reducing leakage power

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Annual International Symposium on computer architecture, ISCA

作者： K. Flautner Nam Sung Kim S. Martin D. Blaauw T. Mudge ARM Ltd Cambridge UK Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA The University of Michigan Advanced Computer Architecture Lab Ann Arbor MI

On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink the dominant component of this power loss will be leakage. However, during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving, low-power drowsy mode. Moving lines into and out of drowsy state incurs a slight performance loss. In this paper we investigate policies and circuit techniques for implementing drowsy caches. We show that with simple architectural techniques, about 80%-90% of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. According to our projections, in a 0.07 um CMOS process, drowsy caches will be able to reduce the total energy (static and dynamic) consumed in the caches by 50%-75%. We also argue that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.

关键词： Dynamic voltage scaling Voltage control Energy consumption computer architecture Circuit simulation Threshold voltage Leakage current Inverters Semiconductor device modeling Predictive models

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A statistical model of input glitch propagation and its application in power macromodeling

A statistical model of input glitch propagation and its appl...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Xun Liu M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Power macromodeling technique can result in huge underestimation without the consideration of input glitches. In this paper, we propose a statistical model for the propagation of input glitches and their effects on circuit power consumption. Based on this model, we develop an analytical power macromodeling approach incorporating input glitches. Specifically, we divide the macromodel parameter space into three regions and characterize each region separately. We have evaluated the proposed technique on ISCAS85 and LGSynth93 benchmark circuits. Compared with switch level simulation results, the average power estimation errors are 1.8% and 3.1% for combinational and sequential circuits, respectively. Our model also provides useful insight for glitchy circuit identification and input glitch power reduction.

关键词： Statistics Table lookup Phase estimation Power dissipation Switches Switching circuits Sequential circuits Signal generators Registers Interpolation

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Design of a high-throughput low-power IS95 Viterbi decoder

Design of a high-throughput low-power IS95 Viterbi decoder

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Design Automation Conference

作者： Xun Liu M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

ISBN: (纸本)1581134614

The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data-transfer oriented design methodology to implement a low-power 256-state rate-1/3 IS95 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the RTL implementation of the individual processors, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 /spl mu/m standard cell library, our decoder achieves a throughput of 20 Mbps in simulation and dissipates only 450 mW.

关键词： Viterbi algorithm Decoding Arithmetic Global communication Wires Energy consumption Design methodology Processor scheduling Design optimization Power dissipation

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Fault-tolerant quantum computers

Fault-tolerant quantum computers

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： John P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering & Computer Science University of Michigan Ann Arbor MI USA

Summary form only given, as follows. Quantum computation is a recently-introduced and novel computing technique which is based on quantum mechanics rather than classical physics. Its starting point is the notion of a quantum bit or "qubit". Because of the superposition property of quantum states, n qubits can store 2n numbers simultaneously, implying a type of massive parallelism. Furthermore, quantum states allow powerful forms of interaction such as entanglement that have no classical counterparts. As a result, quantum computers can solve some important and hitherto intractable problems such as prime factorization of large numbers. However, practical quantum computing circuits are very difficult to construct and they contain far more sources of error than classical circuits. For example, signal states are inherently unstable and tend to decay rapidly due to interaction with the environment, a phenomenon called decoherence. Quantum gates are defined by continuous parameters that allow small errors to arise and propagate to other gates. Furthermore, state measurement is probabilistic and destructive in that the measurement process affects the state being measured. While it is too soon to predict the physical form that quantum computers will eventually take, it is likely that they will incorporate various forms of fault tolerance. This talk will review the basics of quantum computation and the design of fault-tolerant circuits to implement quantum algorithms. In particular, methods for error correction and recovery that have been developed specifically for quantum circuits will be discussed. Finally, the physical implementation of these circuits will be considered, along with the prospects for fault-tolerant quantum computers.

关键词： Quantum computing Fault tolerance Physics computing Quantum mechanics computer errors computer architecture computer science Parallel processing

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Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction

Drowsy instruction caches. Leakage power reduction using dyn...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Nam Sung Kim K. Flautner D. Blaauw T. Mudge Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA ARM Limited Cambridge UK

On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. In our previous work we have shown how the drowsy circuit - a simple, state-preserving, low-leakage circuit that relies on voltage scaling for leakage reduction - can be used to reduce the total energy consumption of data caches by more than 50%. In this paper, we extend the architectural control mechanism of the drowsy cache to reduce leakage power consumption of instruction caches without significant impact on execution time. Our results show that data and instruction caches require different control strategies for efficient execution. To enable drowsy instruction caches, we propose a technique called cache sub-bank prediction which is used to selectively wake up only the necessary parts of the instruction cache, while allowing most of the cache to stay in a low leakage drowsy mode. This prediction technique reduces the negative performance impact by 76% compared to the no-prediction policy. Our technique works well even with small predictor sizes and enables an 86% reduction of leakage energy in a 64 K byte instruction cache.

关键词： Dynamic voltage scaling Tellurium

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TAXI: Trace Analysis for x86 Interpretation

TAXI: Trace Analysis for x86 Interpretation

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： S. Vlaovic E.S. Davidson Sun Microsystems Santa Clara USA Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

Although x86 processors have been around for a long time and are the most ubiquitous processors in the world, the amount of academic research regarding details of their performance has been minimal. We introduce an x86 simulation environment, called TAXI (Trace Analysis for X86 Interpretation), and use it to present results for eight Win32 applications. In this paper, we explain the design and implementation of TAXI.

关键词： Timing Application software Software performance Microarchitecture Hardware Emulation computer architecture Sun Laboratories Computational modeling

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Incorporation of input glitches into power macromodeling

Incorporation of input glitches into power macromodeling

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Xun Liu M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor Michigan

Previous research on power macromodeling has always assumed glitch-free input signals. However, in an actual operating environment, the input signals of a circuit can contain glitches, which are generated by the previous stage of circuitry. In this paper, we investigate the impact of input glitches on the power dissipation of a circuit. Specifically, we show that the frequency and average duration of input glitches are two important factors affecting the overall power consumption. Input glitches can also increase output glitching by a surprisingly large amount. We present a simple yet effective analytical power macromodeling approach incorporating the effects of input glitching. In experiments with ISCAS-85 benchmark circuits, the average error of the proposed technique is 4.44%.

关键词： Power dissipation Frequency Statistics Table lookup Signal generators Energy consumption Signal mapping Circuit simulation computer architecture Power generation

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