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FlashCache: A NAND flash memory file cache for low power web servers

FlashCache: A NAND flash memory file cache for low power web...

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CASES 2006: International Conference on Compilers, architecture and Synthesis for Embedded Systems

作者： Kgil, Taeho Mudge, Trevor Advanced Computer Architecture Laboratory University of Michigan Ann Arbor United States

ISBN: (纸本)1595935436

We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a relatively small DRAM, which includes a primary file buffer cache, and a flash memory secondary file buffer cache. Compared to a conventional DRAM-only architecture, our architecture consumes orders of magnitude less idle power while remaining cost effective. This is a result of using flash memory, which consumes orders of magnitude less idle power than DRAM and is twice as dense. The client request behavior in web servers, allows us to show that the primary drawbacks of flash memory?endurance and long write latencies?can easily be overcome. In fact the wear-level aware management techniques that we propose are not heavily used. Copyright 2006 ACM.

关键词： Flash memory

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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

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CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Fan, Kevin Kudlur, Manjunath Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable. © Copyright 2006 ACM.

关键词： computer hardware

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Streamroller: Automatic synthesis of prescribed throughput accelerator pipelines

Streamroller: Automatic synthesis of prescribed throughput a...

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CODES+ISSS 2006: 4th International Conference on Hardware Software Codesign and System Synthesis

作者： Kudlur, Manjunath Fan, Kevin Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

In this paper, we present a methodology for designing a pipeline of accelerators for an application. The application is modeled using sequential C language with simple stylizations. The synthesis of the accelerator pipeline involves designing loop accelerators for individual kernels, instantiating buffers for arrays used in the application, and hooking up these building blocks to form a pipeline. A compiler-based system automatically synthesizes loop accelerators for individual kernels at varying performance levels. An integer linear program formulation which simultaneously optimizes the cost of loop accelerators and the cost of memory buffers is proposed to compose the loop accelerators to form an accelerator pipeline for the whole application. Cases studies for some applications, including FMRadio and Beamformer, are presented to illustrate our design methodology. Experiments show significant cost savings are achieved through hardware sharing, while achieving the prescribed throughput requirements. © Copyright 2006 ACM.

关键词： Pipeline processing systems

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Protection and restoration scheme for light-trail WDM ring networks

Protection and restoration scheme for light-trail WDM ring n...

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2005 Conference onOptical Network Design and Modelling: Towards the broadband-for-all era, ONDM 2005

作者： Gumaste, Ashwin Zheng, Si Qing Advanced Computer Networks and Architecture Laboratory University of Texas Dallas TX 75083

In this paper we propose a protection strategy for light-trail [1-4] networks for ring topologies. A light-trail is a multi-point lightpath, such that multiple users can take part in communication along the trail, through time (differentiated) non-overlapping connections. Dynamic connections between source-destination pairs can be set up and torn down without the need for optical switch reconfiguration. A light-trail hence represents an opportunistic medium that reduces the uncertainty of provisioning resources for dynamic connections. However, this multi-point flow model leads to a new set of problems in the area of protecting and restoring light-trail based networks. Conventional link protection or path protection techniques are not sufficient for light-trails because of the potential of having multiple possible source-destination pairs in the same trail over time. In this paper we propose a hardware scheme to protect light-trails and further prove its correctness. Further, the scheme is implemented through a failed-traffic assignment algorithm. Subsequently we consider alternative heuristic schemes for implementing the protection scheme proposed. We simulate and compare the simulation results to an analytical model developed. © 2005 IEEE.

关键词： Packet networks

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A dual-processor solution for the MAC layer of a software defined radio terminal

A dual-processor solution for the MAC layer of a software de...

引用

CASES 2005: International Conference on Compilers, architecture, and Synthesis for Embedded Systems

作者： Lee, Hyunseok Mudge, Trevor Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan United States

ISBN: (纸本)159593149X

Considerable work has been devoted to studying flexible computation structures for the physical layer of a software defined radio (SDR) terminal. However there has been almost no research on protocol processors for the upper layer protocols such as the media access control (MAC) and link protocol. A general purpose processor (GPP) is sufficient for the protocol processing of a single mode terminal. However, in the case of a multi-mode system required for SDR, there is a very wide set of possibilities for the MAC layer. In principle these too could be handled by a GPP. However, we show that a better solution is to use a GPP augmented by a small supplemental processor. The GPP is responsible for the relatively complex protocol operations in the active mode, and the supplemental processor handles the idle mode operations. This separation of responsibilities simplifies the implementation of hard real-time responses required by some protocols (for example IEEE 802.11), while maintaining the programmability needed to handle a wide range of protocols. In addition, this organization allows a significant power savings in the idle mode. This is important because the protocol processor must process a large number of tiny idle mode tasks whose aggregate effect over time dominates the power consumption in a wireless terminal. As part of our study we develop a hardware model of the supplemental processor in Verilog and its software model in C. Using commercial CAD tools we synthesized out design and evaluated the power consumption and response time of the platform. Our results show that the proposed platform meets the real-time deadlines at low power while maintaining programmability. Copyright 2005 ACM.

关键词： Microprocessor chips

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A hierarchical approach to modeling and improving the performance of scientific applications on the KSR1

A hierarchical approach to modeling and improving the perfor...

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23rd International Conference on Parallel Processing, ICPP 1994

作者： Boyd, E.L. Azeem, W. Lee, Hsien-Hsin Shih, Tien-Pao Hung, Shih-Hao Davidson, E.S. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan United States

We have developed a hierarchical performance bounding methodology that attempts to explain the performance of loop-dominated scientific applications on particular systems. The Kendall Square Research KSR1 is used as a running example. We model the throughput of key hardware units that arc common bottlenecks in concurrent machines. The four units currently used are: memory port, floating-point, instruction issue, and a loop-carried dependence pseudo-unit. We propose a workload characterization, and derive upper bounds on the performance of specific machine-workload pairs. Comparing delivered performance with bounds focuses attention on areas for improvement and indicates how much improvement might be attainable. We delineate a comprehensive approach to modeling and improving application performance on the KSR1. Application of this approach is being automated for the KSR1 with a series of tools including K-MA and K-MACSTAT (which enable the calculation of the MACS hierarchy of performance bounds), K-Trace (which allows parallel code to be instrumented to produce a memory reference trace), and K-Cache (which simulates inter-cache communications based on a memory reference trace). © 1994 IEEE.

关键词： Hierarchical systems

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Evaluating the communication performance of MPPs using synthetic sparse matrix multiplication workloads 93

Evaluating the communication performance of MPPs using synth...

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7th International Conference on Supercomputing, ICS 1993

作者： Boyd, Eric L. Wellman, John-David Abraham, Santosh G. Davidson, Edward S. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan United States

ISBN: (纸本)089791600X

Communication has a dominant impact on the performance of massively parallel processors (MPPs). We propose a methodology to evaluate the internode communication performance of MPPs using a controlled set of synthetic workloads. By generating a range of sparse matrices and measuring the performance of a simple parallel algorithm that repeatedly multiplies a sparse matrix by a dense vector, we can determine the relative performance of different communication workloads. Specifiable communication parameters include the number of nodes, the average amount of communication per node, the degree of sharing among the nodes, and the computation-communication ratio. We describe a general procedure for constructing sparse matrices that have these desired communication and computation parameters, and apply a range of these synthetic workloads to evaluate the hierarchical ring interconnection and cache-only memory architecture (COMA) of the Kendall Square Research KSR1 MPP. This analysis discusses the impact of the KSR1 architecture on communication performance, highlighting the utility and impact of the automatic update feature. It also investigates the impact of system contention on the performance, particularly how it causes potential updates to be ignored. © 1993 ACM.

关键词： Memory architecture

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Sponge: Portable stream programming on graphics engines

Sponge: Portable stream programming on graphics engines

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Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems

作者： Hormati, Amir Samadi, Mehrzad Woh, Mark Mudge, Trevor Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781450302661

Graphics processing units (GPUs) provide a low cost platform for accelerating high performance computations. The introduction of new programming languages, such as CUDA and OpenCL, makes GPU programming attractive to a wide variety of programmers. However, programming GPUs is still a cumbersome task for two primary reasons: tedious performance optimizations and lack of portability. First, optimizing an algorithm for a specific GPU is a time-consuming task that requires a thorough understanding of both the algorithm and the underlying hardware. Unoptimized CUDA programs typically only achieve a small fraction of the peak GPU performance. Second, GPU code lacks efficient portability as code written for one GPU can be inefficient when executed on another. Moving code from one GPU to another while maintaining the desired performance is a non-trivial task often requiring significant modifications to account for the hardware differences. In this work, we propose Sponge, a compilation framework for GPUs using synchronous data flow streaming languages. Sponge is capable of performing a wide variety of optimizations to generate efficient code for graphics engines. Sponge alleviates the problems associated with current GPU programming methods by providing portability across different generations of GPUs and CPUs, and a better abstraction of the hardware details, such as the memory hierarchy and threading model. Using streaming, we provide a writeonce software paradigm and rely on the compiler to automatically create optimized CUDA code for a wide variety of GPU targets. Sponge's compiler optimizations improve the performance of the baseline CUDA implementations by an average of 3.2x. Copyright © 2011 ACM.

关键词： Graphics processing unit

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Paraprox: Pattern-based approximation for data parallel applications 14

Paraprox: Pattern-based approximation for data parallel appl...

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19th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014

作者： Samadi, Mehrzad Jamshidi, Davoud Anoushe Lee, Janghaeng Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781450323055

Approximate computing is an approach where reduced ac-curacy of results is traded off for increased speed, through-put, or both. Loss of accuracy is not permissible in all computing domains, but there are a growing number of data-intensive domains where the output of programs need not be perfectly correct to provide useful results or even notice-able differences to the end user. These soft domains include multimedia processing, machine learning, and data mining/-analysis. An important challenge with approximate computing is transparency to insulate both software and hardware developers from the time, cost, and difficulty of using approximation. This paper proposes a software-only system, Paraprox, for realizing transparent approximation of data-parallel programs that operates on commodity hardware systems. Paraprox starts with a data-parallel kernel implemented using OpenCL or CUDA and creates a parameterized approximate kernel that is tuned at runtime to maximize performance subject to a target output quality (TOQ) that is supplied by the user. Approximate kernels are created by recognizing common computation idioms found in data-parallel programs (e.g., Map, Scatter/Gather, Reduction, Scan, Stencil, and Partition) and substituting approximate implementations in their place. Across a set of 13 soft data-parallel applications with at most 10% quality degradation, Paraprox yields an average performance gain of 2.7x on a NVIDIA GTX 560 GPU and 2.5x on an Intel Core i7 quad-core processor compared to accurate execution on each platform. Copyright is held by the owner/author(s).

关键词： Graphics processing unit

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Trace based phase prediction for tightly-coupled heterogeneous cores 46

Trace based phase prediction for tightly-coupled heterogeneo...

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46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2013

作者： Padmanabha, Shruti Lukefahr, Andrew Das, Reetuparna Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781450326384

Heterogeneous multicore systems are composed of multiple cores with varying energy and performance characteristics. A controller dynamically detects phase changes in applications and migrates execution onto the most efficient core that meets the performance requirements. In this paper, we show that existing techniques that react to performance changes break down at fine-grain intervals, as performance variations between consecutive intervals are high. We propose a predictive trace-based switching controller that predicts an upcoming phase change in a program and preemptively migrates execution onto a more suitable core. This prediction is based on a phase's individual history and the current program context. Our implementation detects repeatable code sequences to build history, uses these histories to predict an phase change, and preemptively migrates execution to the most appropriate core. We compare our method to phase prediction schemes that track the frequency of code blocks touched during execution as well as traditional reactive controllers, and demonstrate significant increases in prediction accuracy at fine-granularities. For a big-little heterogeneous system that is comprised of a high performing out-of-order core (Big) and an energy-efficient, in-order core (Little), at granularities of 300 instructions, the trace based predictor can spend 28% of execution time on the Little, while targeting a maximum performance degradation of 5%. This translates to an increased energy savings of 15% on average over running only on Big, representing a 60% increase over existing techniques. © 2013 ACM.

关键词： Energy efficiency

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