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Stack value file: custom microarchitecture for the stack

Stack value file: custom microarchitecture for the stack

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IEEE Symposium on High-Performance computer architecture

作者： H.H.-S. Lee M. Smelyanskiy C.J. Newburn G.S. Tyson Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA PMD Architecture Intel Corporation Portland OR USA

ISBN: (纸本)0769510191

As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed partitioning the cache into instruction/data, temporal/non-temporal, and/or stack/non-stack regions. Each of these designs can improve performance by constructing two separate structures which can be probed in parallel while reducing contention. In this paper, we propose a new memory organization that partitions data references into stack and nonstack regions. Non-stack references are routed to a conventional cache. Stack references, on the other hand, are shown to have several characteristics that can be leveraged to improve performance using a less conventional storage organization. This paper enumerates those characteristics and proposes a new microarchitectural feature, the stack value file (SVF), which exploits them to improve instruction-level parallelism, reduce stack access latencies, reduce demand on the first-level cache, and reduce data bus traffic. Our results show that the SVF can improve execution performance by 29 to 65% while reducing overhead traffic for the stack region by many orders of magnitude over cache structures of the same size.

关键词： Microarchitecture computer architecture Registers Parallel processing Delay Time factors History Performance evaluation

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Multiresolution time domain modeling for large scale wireless communication problems

Multiresolution time domain modeling for large scale wireles...

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Antennas and Propagation Society International Symposium

作者： C.D. Sarris K. Tomko P. Czarnul Shih-Hao Hung R.L. Robertson Donghoon Chun E.S. Davidson L.P.B. Katehi Radiation Laboratory EECS University of Michigan Ann Arbor USA Department of Electrical and Computer Engineering and Computer Science University of Cincinnati USA Advanced Computer Architecture Laboratory EECS University of Michigan Ann Arbor USA

The time domain modeling of large scale cosite interference problems, arising in wireless communication channel analysis and design studies, is discussed. It is pointed out that the use of the conventional finite difference time domain method for the treatment of such problems typically results in long, computationally burdensome simulations that limit the ability of this technique to provide an efficient CAD-oriented tool for commercial and military applications. For the purpose of accelerating these simulations, the use of wavelet based time domain solvers along with parallelization techniques is proposed.

关键词： Large-scale systems Wireless communication Finite difference methods Time domain analysis Laboratories Equations Signal resolution computer science computer architecture Design automation

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Reconfigurable low energy multiplier for multimedia system design

Reconfigurable low energy multiplier for multimedia system d...

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IEEE computer Society Workshop on VLSI, IWV 2000

作者： Kim, S. Papaefthymiou, M.C. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109 United States

ISBN: (纸本)0769505341

This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multiplier architecture, we have designed a multiplier-based inverse quantizer (IQ) for MPEG-2 MP@ML. Pipelines are dynamically reconfigured according to the size of the picture and the number of nonzero quantized DCT coefficients per block. In comparison with corresponding multiplier implementations that use conventional pipelines, our reconfigurable multipliers dissipate about 31-58% less energy. Relative energy savings increase with decreasing data rates, since our reconfigurable structures stay in a low energy configuration for proportionately longer time. © 2000 IEEE.

关键词： Pipelines

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Dynamic memory design for low data-retention power 10th

引用

10th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000

作者： Kim, Joohee Papaefthymiou, Marios C. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109 United States

ISBN: (纸本)9783540410683

The emergence of data-intensive applications in mobile environments has resulted in portable electronic systems with increasingly large dynamic memories. The typical operating pattern exhibited by these applications is a relatively short burst of operations followed by longer periods of standby. Due to their periodic refresh requirements, dynamic memories consume substantial power even during standby and thus have a significant impact on battery lifetime. In this paper we investigate a methodology for designing dynamic memory with low data-retention power. Our approach relies on the fact that the refresh period of a memory array is dictated by only a few, worst-case leaky cells. In our scheme, multiple refresh periods are used to reduce energy dissipation by selectively refreshing only the cells that are about to lose their stored values. Additional energy savings are achieved by using error-correction to restore corrupted cell values and thus allow for extended refresh periods. We describe an exact O(nk−1)-time algorithm that, given a memory array with n refresh blocks and two positive integers k and l, computes k refresh periods that maximize the average refresh period of a memory array when refreshing occurs in blocks of l cells. In simulations with 16Mb memory arrays and a (72,64) modified Hamming single-error correction code, our scheme results in an average refresh period of up to 11 times longer than the original refresh period. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Energy dissipation

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Improving BTB performance in the presence of DLLs

Improving BTB performance in the presence of DLLs

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： S. Vlaovic E.S. Davidson G.S. Tyson Advanced Computer Architecture Laboratory University of Michigan USA

Dynamically Linked Libraries (DLLs) promote software modularity, portability, and flexibility and their use has become widespread. The authors characterize the behavior of five applications that make heavy use of DLLs, with a particular focus on the effects of DLLs on Branch Target Buffer (BTB) performance. DLLs aggravate hot set contention in the BTB. Standard software remedies are ineffective because the DLLs are shared, compiled separately, and dynamically linked to applications. We propose a hardware technique, the DLL BTB, that adds a small second buffer to the BTB and dedicates it to storing DLL target addresses. We show that the DLL BTB performance is similar to a BTB with a victim buffer, but the DLL BTB requires no parallel lookups or datapaths between the original BTB and the added buffer.

关键词： Hardware Software libraries Buffer storage Software performance Application software Etching computer architecture Kernel Runtime environment Memory management

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The store-load address table and speculative register promotion

The store-load address table and speculative register promot...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： M. Postiff D. Greene T. Mudge Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot always prove that a value is free of aliases, and thus promotion cannot always be applied. This paper proposes a new hardware structure, the store-load address table (SLAT), which watches both load and store instructions to see if they conflict with entries loaded into the SLAT by explicit software mapping instructions. One use of the SLAT is to allow values to be promoted to registers when they cannot be proven to be promotable by conventional compiler analysis. We call this new optimization speculative register promotion. Using this technique, a value can be promoted to a register and aliased loads and stores to that value's home memory location are caught and the proper fixup is performed. This paper will: a) describe the SLAT hardware and software; b) demonstrate that conventional register promotion is often inhibited by static compiler analysis; c) describe the speculative register promotion optimization; and d) quantify the performance increases possible when a SLAT is used. Our results show that for certain benchmarks, up to 35% of loads and 15% of stores can potentially be eliminated by using the SLAT.

关键词： Registers Hardware Optimizing compilers Program processors computer architecture Laboratories Watches Performance gain

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Reconfigurable low energy multiplier for multimedia system design

Reconfigurable low energy multiplier for multimedia system d...

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IEEE computer Society Workshop on VLSI

作者： S. Kim M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

关键词： Multimedia systems Pipeline processing Discrete cosine transforms Throughput Energy dissipation Energy efficiency Energy consumption Voltage Clocks Registers

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A fully associative software-managed cache design

A fully associative software-managed cache design

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Annual International Symposium on computer architecture, ISCA

作者： E.G. Hallnor S.K. Reinhardt Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

As DRAM access latencies approach a thousand instruction-execution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue to be appropriate. Two key features-full associativity and software management-have been used successfully in the virtual-memory domain to cope with disk access latencies. Future systems will need to employ similar techniques to deal with DRAM latencies. This paper presents a practical, fully associative, software-managed secondary cache system that provides performance competitive with or superior to traditional caches without OS or application involvement. We see this structure as the first step toward OS- and application-aware management of large on-chip caches. This paper has two primary contributions a practical design for a fully associative memory structure, the indirect index cache (IIC), and a novel replacement algorithm, generational replacement, that is specifically designed to work with the IIC. We analyze the behavior of an IIC with generational replacement as a drop-in, transparent substitute for a conventional secondary cache. We achieve miss rate reductions from 8% to 85% relative to a 4-way associative LRU organization, matching or beating a (practically infeasible) fully associative true LRU cache. Incorporating these miss rates into a rudimentary timing model indicates that the IIC/generational replacement cache could be competitive with a conventional cache at today's DRAM latencies, and will outperform a conventional cache as these CPU-relative latencies grow.

关键词： Random access memory Delay Algorithm design and analysis Microprocessors Prefetching computer architecture Laboratories computer science Aging Application software

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The store-load address table and speculative register promotion 33

The store-load address table and speculative register promot...

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Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

作者： Matthew Postiff David Greene Trevor Mudge Advanced Computer Architecture Laboratory University of Michigan 1301 Beal Ave. Ann Arbor MI

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A fully associative software-managed cache design 00

A fully associative software-managed cache design

引用

Proceedings of the 27th annual international symposium on computer architecture

作者： Erik G. Hallnor Steven K. Reinhardt Advanced Computer Architecture Laboratory Dept. of Electrical Engineering and Computer Science The University of Michigan 1301 Beal Ave. Ann Arbor MI

ISBN: (纸本)9781581132328

As DRAM access latencies approach a thousand instruction-execution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue to be appropriate. Two key features—full associativity and software management—have been used successfully in the virtual-memory domain to cope with disk access latencies. Future systems will need to employ similar techniques to deal with DRAM latencies. This paper presents a practical, fully associative, software-managed secondary cache system that provides performance competitive with or superior to traditional caches without OS or application involvement. We see this structure as the first step toward OS- and application-aware management of large on-chip *** paper has two primary contributions: a practical design for a fully associative memory structure, the indirect index cache (IIC), and a novel replacement algorithm, generational replacement, that is specifically designed to work with the IIC. We analyze the behavior of an IIC with generational replacement as a drop-in, transparent substitute for a conventional secondary cache. We achieve miss rate reductions from 8% to 85% relative to a 4-way associative LRU organization, matching or beating a (practically infeasible) fully associative true LRU cache. Incorporating these miss rates into a rudimentary timing model indicates that the IIC/generational replacement cache could be competitive with a conventional cache at today's DRAM latencies, and will outperform a conventional cache as these CPU-relative latencies grow.

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