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VLSI Test Symposium

作者： H. Al-Asaad J.P. Hayes Dept. of Electr. & Comput. Eng. California Univ. Davis CA USA Advanced Computer Architecture Laboratory Department of Electrical Engineering & Computer Science University of Michigan Ann Arbor MI USA

ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of simulation algorithms based on parallel-pattern evaluation, multiple error activation, single fault propagation, and critical path tracing. Several experiments are discussed to demonstrate the power of ESIM.

关键词： Circuit faults Circuit simulation Logic circuits computer errors Circuit testing Computational modeling computer simulation Error correction Design engineering Laboratories

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DIVA: a reliable substrate for deep submicron microarchitecture design 32

DIVA: a reliable substrate for deep submicron microarchitect...

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Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture

作者： Todd M. Austin Advanced Computer Architecture Laboratory University of Michigan

ISBN: (纸本)9780769504377

Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To further complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation *** this paper, we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. The functional checker verifies the correctness of the core processor's computation, only permitting correct results to commit. Overall design cost can be dramatically reduced because designers need only verify the correctness of the checker *** detail the DIVA checker architecture, a design optimized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA checkers have little impact on core processor performance. To make the case for reduced verification costs, we argue that the DIVA checker should lend itself to functional and electrical verification better than a complex core processor. Finally, future applications that leverage dynamic verification to increase processor performance and availability are suggested.

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DIVA: a reliable substrate for deep submicron microarchitecture design

DIVA: a reliable substrate for deep submicron microarchitect...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： T.M. Austin Advanced Computer Architecture Laboratory University of Michigan USA

Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To further complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation interference. In this paper, we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. The functional checker verifies the correctness of the core processor's computation, only permitting correct results to commit. Overall design cost can be dramatically reduced because designers need only verify the correctness of the checker unit. We detail the DIVA checker architecture, a design optimized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA checkers have little impact on core processor performance. To make the case for reduced verification costs, we argue that the DIVA checker should lend itself to functional and electrical verification better than a complex core processor. Finally, future applications that leverage dynamic verification to increase processor performance and availability are suggested.

关键词： Microarchitecture Microprocessors Cost function Buildings Fabrication Degradation Logic Interference Pipelines computer architecture

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Pipelined DSP design with a true single-phase energy-recovering logic style

Pipelined DSP design with a true single-phase energy-recover...

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IEEE Alessandro Volta Memorial Workshop on Low-Power Design

作者： S. Kim M.C. Papaefthymiou Advanced Computer Architecture Laboratory Ann Arbor MI USA

We recently invented a true single-phase energy-recovering circuit family, called TSEL, that relies on a cross-coupled latch structure and two DC reference voltages to achieve low energy consumption for a broad range of operating frequencies. In this paper, we explore the application of TSEL to the design of low-energy DSP circuits. Specifically, we describe and evaluate a 6,768-transistor, pipelined TSEL module that performs the 8-point Hadamard transform. In layout simulations with a standard 0.5 /spl mu/m CMOS technology, our TSEL module functions correctly for operating frequencies in excess of 280 MHz. Above 40 MHz, our TSEL design is more energy-efficient than any other energy-recovering alternative with a similar cross-coupled latch structure. At 280 MHz; it is at least 4 times more energy-efficient than a corresponding static CMOS design.

关键词： Digital signal processing Logic design Power supplies Clocks Voltage

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Crosstalk constrained global route embedding 99

Crosstalk constrained global route embedding

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Proceedings of the 1999 international symposium on Physical design

作者： Phiroze N. Parakh Richard B. Brown Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan

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Single-phase source-coupled adiabatic logic 99

Single-phase source-coupled adiabatic logic

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Suhwan Kim M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

ISBN: (纸本)9781581131338

Adiabatic circuits offer a promising alternative to conventional circuitry for low energy design. Their operation is nevertheless subject to fundamental energy-speed trade-offs, just like any other physical realization of boolean logic. Thus, adiabatic circuits with very low energy consumption at low frequencies fail to function at high operating frequencies. Conversely, high-speed adiabatic circuits tend to be dissipative at low clock rates. This paper describes SCAL, a single-phase source-coupled adiabatic logic family that operates efficiently across a wide range of operating frequencies. In layout-based simulations with 0.5 /spl mu/m CMOS process parameters, pipelined carry-lookahead adders developed in our logic function correctly from 10 MHz up to 280 MHz. Our SCAL adders are less dissipative than corresponding designs in alternative adiabatic families that remain functional across the same frequency range. Moreover, they are about as dissipative as other adiabatic circuits that are geared towards very efficient operation at low frequencies. In comparison with their CMOS counterparts, our SCAL adders are 3 to 10 times more energy efficient.

关键词： Frequency Adders Boolean functions VHF circuits Energy consumption Clocks CMOS logic circuits Circuit simulation CMOS process Logic functions

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Delay fault testing of designs with embedded IP cores

Delay fault testing of designs with embedded IP cores

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VLSI Test Symposium

作者： Hyungwon Kim J.P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Conventional methods cannot effectively verify path delays of designs employing IP circuits (cores) whose implementation details are hidden. A delay fault ATPG method for such designs is proposed that employs a scan technique called selectively transparent scan (STS). Experimental results are presented which show that the STS method can robustly test paths of a specified delay range in core-based circuits, and substantially reduce test length.

关键词： Circuit testing Circuit faults Sociotechnical systems System testing Registers System-on-a-chip Delay effects Automatic test pattern generation Design methodology Intellectual property

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Superconducting processors for HTMT: issues and challenges

Superconducting processors for HTMT: issues and challenges

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Frontiers of Massively Parallel Computation

作者： K.B. Theobald G.R. Gao T.L. Sterling Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering University of Delaware Newark DE USA NASA Jet Propulsion Laboratory /Center for Advanced Computing Research California Institute of Technology Pasadena CA USA

The Hybrid Technology Multi-Threading project is a long-term study of the feasibility of combining several emerging technologies to reach 1 petaFLOPS within ten years. HTMT will combine high-speed superconductor processors, semiconductor memories with built-in processors, high-speed optical interconnects, and high-density holographic storage. While there are major challenges in all aspects of this project, those in processor architecture are the focus of this paper. Fundamental differences between RSFQ circuits and conventional semiconductor circuits, including a radical jump in clock speed, make today's processor design approaches inappropriate for HTMT. Sequential instruction dispatching, even within the lowest programming unit (a strand), will lead to unacceptably high latencies, hence poor performance. We propose alternative processor designs which use fine-grain synchronizations between individual instructions in order to avoid these bottlenecks.

关键词： Random access memory Optical buffering Holography Holographic optical components Delay computer architecture Optical interconnections Electrical capacitance tomography Quantum computing Clocks

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System support for dynamic optimization of application performance

System support for dynamic optimization of application perfo...

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1998 International Workshop on Innovative architecture, IWIA 1998

作者： Hung, Shih-Hao Davidson, Edward S. Advanced Computer Architecture Laboratory University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0769501257

Today's high performance and parallel computer systems provide substantial opportunities for concurrency of execution and scalability that is largely untapped by the applications that run on them. Under traditional frameworks, developing efficient applications can be a labor-intensive process that requires an intimate knowledge of the machines, the applications, and many subtle machine-application interactions. Optimizing applications so that they can achieve their full potential on target machines is often beyond the programmer's or the compiler's ability or endurance. This paper argues for addressing the performance optimization problem by providing support for tuning application codes with substantially reduced human intervention by exploiting dynamic information gathered at run time so that the optimization is responsive to actual run time behavior as data sets change and installed systems evolve. © 1999 IEEE.

关键词： Application tuning Compiler optimization Performance evaluation

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The edge-based design rule model revisited

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ACM Transactions on Design Automation of Electronic Systems 1998年第3期3卷 463-486页

作者： Riepe, Michael A. Sakallah, Karem A. University of Michigan Ann Arbor MI 48109-2122 United States Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109-2122 1301 Beal Avenue United States

A model for integrated circuit design rules based on rectangle edge constraints has been proposed by Jeppson, Christensson, and Hedenstierna. This model appears to be the most rigorous proposed to date for the description of such edge-based design rules. However, in certain rare circumstances their model is unable to express the correct design rule when the constrained edges are not adjacent in the layout. We introduce a new notation, called an edge path, which allows us to extend their model to allow for constraints between edges separated by an arbitrary number of intervening edges. Using this notation we enumerate all edge paths that are required to correctly model the original design rule macros of the JCH model, and prove that these macros are sufficient to model the most common rules. We also show how this notation allows us to directly specify many kinds of conditional design rules that required ad hoc specification under the JCH model. © 1999 ACM.

关键词： Design rule checking Design rules Layout verification Theory Verification

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