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Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance 98

Effects of architectural and technological advances on the H...

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Proceedings of the 25th annual international symposium on computer architecture

作者： Gheith A. Abandah Edward S. Davidson Advanced Computer Architecture Laboratory University of Michigan Ann Arbor

ISBN: (纸本)9780818684913

Advances in microarchitecture, packaging, and manufacturing processes enable designers to build new systems with higher performance and scalability. Using microbenchmark techniques, we contrast the memory and communication performance of two generations of the HP/Convex Exemplar scalable parallel processing system. The SPP1000 and SPP2000 have significant architectural and implementation differences, but maintain upward binary compatibility. The SPP2000 employs manufacturing and packaging advances to obtain shorter system interconnects with wider data paths and improved functionality, thereby reducing the latency and increasing the bandwidth of remote communication. Although the memory latency is not significantly improved, newer out-of-order execution processors coupled with nonblocking caches achieve much higher memory bandwidth. The SPP2000 has a richer system interconnect topology that allows scalability to a larger number of processors. The SPP2000 also employs innovations in its coherence protocols to improve synchronization and communication performance. This paper characterizes the performance effects of these changes, and identifies some remaining inefficiencies, in the cache coherence protocol and the node configuration, that future systems should address.

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Configuration independent analysis for characterizing shared-memory applications

Configuration independent analysis for characterizing shared...

引用

International Symposium on Parallel Processing

作者： G.A. Abandah E.S. Davidson Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

The paper demonstrates that configuration independent analysis of shared memory applications is useful tool to characterize inherent application characteristics that do not change from one machine configuration to another. Although traditional configuration dependent analysis, or simulation, may directly provide more information about performance on specific configurations, it requires developing a machine model and repeating the analysis for each target configuration. A judicious combination of the two constitutes a comprehensive and efficient methodology. The authors use configuration independent analysis to characterize seven aspects of application behavior: general characteristics; working sets; concurrency; communication patterns; variation over time, and locality; and sharing behavior. Case studies of eight scientific and commercial benchmarks are used to illustrate the advantages and limitations of this approach.

关键词： Application software Performance analysis Information analysis Analytical models Concurrent computing Predictive models computer architecture Laboratories Computational modeling Pattern analysis

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Effects of architectural and technological advances on the HP/Convex Exemplar's memory and communication performance

Effects of architectural and technological advances on the H...

引用

Annual International Symposium on computer architecture, ISCA

作者： G.A. Abandah E.S. Davidson Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

Advances in microarchitecture, packaging, and manufacturing processes enable designers to build new systems with higher performance and scalability. Using microbenchmark techniques, we contrast the memory and communication performance of two generations of the HP/Convex Exemplar scalable parallel processing system. The SPP1000 and SPP2000 have significant architectural and implementation differences, but maintain upward binary compatibility. The SPP2000 employs manufacturing and packaging advances to obtain shorter system interconnects with wider data paths and improved functionality thereby reducing the latency and increasing the bandwidth of remote communication. Although the memory latency is not significantly improved, newer out-of-order execution processors coupled with nonblocking caches achieve much higher memory bandwidth. The SPP2000 has a richer system interconnect topology that allows scalability to a larger number of processors. The SPP2000 also employs innovations in its coherence protocols to improve synchronization and communication performance. This paper characterizes the performance effects of these changes, and identifies some remaining inefficiencies, in the cache coherence protocol and the node configuration, that future systems should address.

关键词： Packaging Scalability Delay Bandwidth Protocols Microarchitecture Manufacturing processes Process design Parallel processing Out of order

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System support for dynamic optimization of application performance

System support for dynamic optimization of application perfo...

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International Workshop on Innovative architecture for Future Generation High-Performance Processors and Systems

作者： Shih-Hao Hung E.S. Davidson Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Today's high performance and parallel computer systems provide substantial opportunities for concurrency of execution and scalability that is largely untapped by the applications that run on them. Under traditional frameworks, developing efficient applications can be a labor-intensive process that requires an intimate knowledge of the machines, the applications, and many subtle machine-application interactions. Optimizing applications so that they can achieve their full potential on target machines is often beyond the programmer's or the compiler's ability or endurance. This paper argues for addressing the performance optimization problem by providing support for tuning application codes with substantially reduced human intervention by exploiting dynamic information gathered at run time so that the optimization is responsive to actual run time behavior as data sets change and installed systems evolve.

关键词： Application software Concurrent computing Optimizing compilers Scalability Performance analysis computer architecture Program processors Humans Hardware Information analysis

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Improving trace cache effectiveness with branch promotion and trace packing 98

Improving trace cache effectiveness with branch promotion an...

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Proceedings of the 25th annual international symposium on computer architecture

作者： Sanjay Jeram Patel Marius Evers Yale N. Patt Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor Michigan

ISBN: (纸本)9780818684913

The increasing widths of superscalar processors are placing greater demands upon the fetch mechanism. The trace cache meets these demands by placing logically contiguous instructions in physically contiguous storage. As a result, the trace cache delivers instructions at a high rate by supplying multiple fetch blocks each *** this paper, we examine two techniques to improve the number of instructions delivered each cycle by the trace cache. The first technique, branch promotion, dynamically converts strongly biased branches into branches with static predictions. Because these promoted branches require no dynamic prediction, the branch predictor suffers less from the negative effects of *** promotion unlocks the potential of the second technique: trace packing. With trace packing, trace segments are packed with as many instructions as will fit, without regard to naturally occurring fetch block boundaries. With both techniques, the effective fetch rate of the trace cache jumps up 17% over a trace cache which implements *** a machine where the execution engine has a very aggressive memory disambiguator, the performance of a machine using branch promotion and trace packing is on average 11% higher than a machine using neither technique.

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Improving trace cache effectiveness with branch promotion and trace packing

Improving trace cache effectiveness with branch promotion an...

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Annual International Symposium on computer architecture, ISCA

作者： S.J. Patel M. Evers Y.N. Patt Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The increasing widths of superscalar processors are placing greater demands upon the fetch mechanism. The trace cache meets these demands by placing logically contiguous instructions in physically contiguous storage. As a result, the trace cache delivers instructions at a high rate by supplying multiple fetch blocks each cycle. In this paper we examine two techniques to improve the number of instructions delivered each cycle by the trace cache. The first technique, branch promotion, dynamically converts strongly biased branches into branches with static predictions. Because these promoted branches require no dynamic prediction, the branch predictor suffers less from the negative effects of interference. Branch promotion unlocks the potential of the second technique: trace packing. With trace packing, trace segments are packed with as many instructions as will fit, without regard to naturally occurring fetch block boundaries. With both techniques, the effective fetch rate of the trace cache jumps up 17% over a trace cache which implements neither on a machine where the execution engine has a very aggressive memory disambiguator; the performance of a machine using branch promotion and trace packing is on average 11% higher than a machine using neither technique.

关键词： Engines Bandwidth Etching computer architecture Laboratories Electronic switching systems Read only memory Electrical capacitance tomography Cache storage Decoding

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Analyzing the working set characteristics of branch execution

Analyzing the working set characteristics of branch executio...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： S.P. Kim G.S. Tyson Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

To achieve highly accurate branch prediction, it is necessary not only to allocate more resources to branch prediction hardware but also to improve the understanding of branch execution characteristics. In this paper, we present a new profile-based conditional branch analysis technique called branch working set analysis to provide additional information about control flow behavior of general purpose applications. This analysis evaluates the dynamic behavior of branch execution by partitioning either individual branches or pre-classified branch groups into sets based on temporal locality and ordering information. We refer to these sets as the working sets of branches. To demonstrate the usefulness of this form of analysis, we examine the efficiency of current allocation techniques for branch history table (BHT) space and propose a new solution to this allocation process that improves the performance of these tables. In our approach the mapping between branch instructions and BHT entries is specified during compilation to reduce table contention-leading to more relevant histories and improved predictor performance. As a result, even for programs with a large number of static branches, only 100 to 200 history entries are needed to approximate the performance of larger 1024-entry BHT. Furthermore, when the technique is applied to a predictor with 1024-entry BHT its prediction accuracy is improved by 16%-comparable with the performance of a BHT of infinite capacity.

关键词： Information analysis History Accuracy Performance analysis computer architecture Laboratories Hardware Research and development Program processors Microarchitecture

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mlcache: a flexible multi-lateral cache simulator

mlcache: a flexible multi-lateral cache simulator

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International Symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： E.S. Tam J.A. Rivers G.S. Tyson E.S. Davidson Advanced Computer Architecture Laboratory Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA

As the gap between processor and memory speeds increases, cache performance becomes more critical to overall system performance. Multi-lateral cache designs such as the Assist, Victim, and NTS cache have been shown to perform as well as or better than larger, single structure caches. Unlike current cache simulators, mlcache (an event-driven, timing-sensitive simulator based on the Latency Effects cache timing model) can evaluate a variety of multilateral cache configurations. It was developed to help designers in the middle of the design cycle decide which cache configuration would best meet the performance needs of the target processor. It can easily model various cache configurations by using its library of cache state and data movement routines. We use the SPEC95 benchmarks to illustrate how mlcache can be used to compare the performance of several different data cache configurations.

关键词： Rivers Reduced instruction set computing Timing Personal communication networks Prefetching Design methodology Space exploration Microprocessors Documentation

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Evaluating the performance of active cache management schemes

Evaluating the performance of active cache management scheme...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： E.S. Tam J.A. Rivers V. Srinivasan G.S. Tyson E.S. Davidson Advanced Computer Architecture Laboratory Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA

In this paper we examine the performance of two multi-lateral cache schemes; one makes block allocation decisions correlated to the reference behavior of regions of memory (NTS), the other correlated to the reference behavior of memory accessing instructions (PCS). To determine the efficacy of exploiting these reference correlation schemes to improve cache management, we compare the performance of these multi-lateral schemes to a multi-lateral configuration that uses a near-optimal (but non-implementable) replacement policy, pseudo-opt. In addition to miss ratio, three metrics are used to evaluate the performance of these schemes, relative to pseudo-opt: 1) prediction accuracy in determining reference locality, 2) actual usage accuracy, i.e. how likely a block in an implementable scheme and the near-optimal scheme exhibit the same reuse characteristic, and 3) tour length of a line in the cache. Results show that while the NTS and PCS schemes outperform traditional cache management schemes, they fall short of the pseudo-opt performance; this is due to their simple prediction strategies and because their active management addresses only block allocation and not replacement.

关键词： Personal communication networks Accuracy Clocks Rivers computer architecture Laboratories Velocity measurement Time measurement Cache memory Information management

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Asymptotically efficient retiming under setup and hold constraints

Asymptotically efficient retiming under setup and hold const...

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IEEE International Conference on computer-Aided Design

作者： M.C. Papaefthymiou Advanced Computer Architecture Laboratory Department of Electrical Engineering arid Computer Science University of Michigan Ann Arbor MI USA

We present a polynomial-time algorithm for retiming synchronous circuits with edge-triggered registers under setup and hold constraints. Given a circuit G and a target clock period c, our algorithm computes in O(V/sup 3/ E) steps a retimed circuit that achieves c and is free of hold violations, where V is the circuit's gate count, and E is the number of wires in the circuit. This is the first polynomial-time algorithm ever reported for retiming with constraints on both long and short paths. The asymptotically efficient operation of our algorithm is based on a novel formulation of the timing constraints as an integer monotonic program with O(E/sup 2/) inequalities.

关键词： Clocks Polynomials Delay Registers Wires Combinational circuits Timing Logic testing Circuit testing Permission

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