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Annual International Symposium on computer architecture, ISCA

作者： Yinong Zhang G.B. Adams Advanced Architecture Laboratory Advanced Micro Devices Inc. Austin TX USA School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

DS (Decoupled-Superscalar) is a new microarchitecture that combines decoupled and superscalar techniques to exploit instruction level parallelism. Issue bandwidth is increased while circuit complexity growth is controlled with little negative impact on performance. Programs for DS are compiled into two instruction substreams: the dominant substream navigates the control flow and the rest of computational task is shared between the dominant and subsidiary substreams. Each substream is processed by a separate superscalar core realizable with current VLSI technology. DS machines are binary compatible with superscalar machines having the same instruction set, and a family of DS machines is binary compatible without recompilation. DS run time behavior is examined with an analytical model. A novel technique for controlling slip between substreams is introduced. Code partitioning issues of instruction count balancing and residence time balancing, important to any split-stream scheme, are discussed. Simulation shows DS achieves performance comparable to an aggressive superscalar, but with potentially less complex hardware and faster clock rate.

关键词： Microarchitecture Parallel processing Bandwidth Complexity theory Navigation computer aided instruction Very large scale integration Analytical models Hardware Clocks

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Origin 2000 design enhancements for communication intensive applications 98

Origin 2000 design enhancements for communication intensive ...

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： G.A. Abandah E.S. Davidson Department of Electrical Engineering University of Jordan Amman Jordan Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780818685910

The SGI Origin 2000 is designed to support a wide range of applications and has low local and remote memory latencies. However it often has a high ratio of remote to local misses. In this paper, we evaluate the Origin 2000 performance with communication intensive applications. We use detailed execution-driven simulation of six shared-memory applications. This paper evaluates a base, Origin 2000-like system and three derived systems that incorporate techniques to reduce the communication cost by lowering the ratio of remote misses. We show that the performance of these applications is generally improved when the local bus is used in the snoopy mode, the number of processors per node is increased, the processors use the Illinois cache coherence protocol, or when adding a snoopy cache to retain remote data within each node. Illinois protocol and the interconnect cache reduce the average remote miss ratio by 16% and 21%, respectively.

关键词： Costs Delay Application software Traffic control Access protocols computer architecture Laboratories Context

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Realistic delay modeling in satisfiability-based timing analysis

Realistic delay modeling in satisfiability-based timing anal...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： L.G. e Silva J.P. Marques Silva L.M. Silveira K.A. Sakallah Cadence European Laboratories/INESC Instituto Superior Technico Lisboa Portugal Electrical Engineering and Computer Science Department Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

Circuit delay computation taking into account the existence of false paths represents a significant and computationally complex problem. Existing research work has focused mainly on path sensitization models and algorithms, and on gate and interconnect delay models. Nevertheless, work in these two main areas has evolved separately, and so most path sensitization models and algorithms assume very rudimentary gate and interconnect delay models. In this paper we propose a modeling framework for circuit delay computation as a sequence of instances of propositional satisfiability. This framework is used to capture several path sensitization models under the unit delay model. Moreover several algorithms for propositional satisfiability are evaluated seeking to illustrate the computational challenges posed by the circuit delay computation problem. Finally, realistic delay models taking into account extracted interconnect delays and fanout data are incorporated into the proposed circuit delay computation framework in order to experimentally evaluate its application.

关键词： Timing Delay estimation Combinational circuits Integrated circuit interconnections Laboratories Data mining Digital circuits Clocks Frequency estimation Sequential circuits

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Event propagation conditions in circuit delay computation

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ACM Transactions on Design Automation of Electronic Systems 1997年第3期2卷 249-280页

作者： Yalcin, Hakan Hayes, John P. Advanced Computer Architecture Laboratory Department Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109-2122 United States

Accurate and efficient computation of delays is a central problem in computer-aided design of complex VLSI circuits. Delays are determined by events (signal transitions) propagated from the inputs of a circuit to its outputs, so precise characterization of event propagation is required for accurate delay computation. Although many different propagation conditions (PCs) have been proposed for delay computation, their properties and relationships have been far from clear. We present a systematic analysis of delay computation based on a series of waveform models that capture signal behavior rigorously at different levels of detail. The most general model, called the exact or W0 model, specifies each event occurring in a circuit signal. A novel method is presented that generates approximate waveforms by progressively eliminating signal values from the exact model. For each waveform model, we derive the PCs that correctly capture the requirements under which an event propagates along a path. The waveform models and their PCs are shown to form a well-defined hierarchy, which provides a means to trade accuracy for computational effort. The relationships among the derived PCs and existing ones are analyzed in depth. It is proven that though many PCs, such as the popular floating mode condition, produce a correct upper bound on the circuit delay, they can fail to recognize event propagation in some instances. This analysis further enables us to derive new and useful PCs. We describe such a PC, called safe static. Experimental results demonstrate that safe static provides an excellent accuracy/efficiency tradeoff. © 1997 ACM.

关键词： Delay computation Event propagation False path Path sensitization Performance Propagation condition Theory Timing analysis Verification Waveform modeling

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Software-managed address translation

Software-managed address translation

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IEEE Symposium on High-Performance computer architecture

作者： B. Jacob T. Mudge Advanced Computer Architecture Laboratory EECS Department University of Michigan USA

In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that software-managed address translation is just as efficient as hardware-managed address translation and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction (CPI) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms.

关键词： Hardware Memory management Operating systems Energy management Power system management Clocks Protection computer architecture Magnetic heads Jacobian matrices

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Timing verification of sequential domino circuits 96

Timing verification of sequential domino circuits

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Proceedings of the 1996 IEEE/ACM international conference on computer-aided design

作者： David Van Campenhout Trevor Mudge Karem A. Sakallah Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann Arbor Michigan

ISBN: (纸本)9780818675973

Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An important observation is that input signals to domino gates may start changing near the end of the evaluate phase. The first method models domino gates explicitly, similar to latches. The second method treats domino gates only during pre- and post-processing steps. This method is shown to be more conservative, but easier to compute.

关键词： domino gates

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An approximate timing analysis method for datapath circuits 96

An approximate timing analysis method for datapath circuits

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Proceedings of the 1996 IEEE/ACM international conference on computer-aided design

作者： Hakan Yalcin John P. Hayes Karem A. Sakallah Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI

ISBN: (纸本)9780818675973

We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier, the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined control inputs, which results in significant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverse-engineered high-level versions of the ISCAS-85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy.

关键词： Approximate timing analysis hierarchical timing models signal propagation conditions. delay calculation conditional delay matrix

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On effective data supply for multi-issue processors

On effective data supply for multi-issue processors

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： J.A. Rivers E.S. Tam E.S. Davidson Advanced Computer Architecture Laboratory Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA

Emerging multi-issue microprocessors require effective data supply to sustain multiple instruction processing. The data cache structure, the backbone of data supply, has been organized and managed as one large homogenous resource, offering little flexibility for selective caching. While memory latency hiding techniques and multi-ported caches are critical to effective data supply, we show in this paper that even ideal non-blocking multi-ported caches fail to be sufficient in and of themselves in supplying data. We evaluate an approach in which the first level (L1) data cache is partitioned into multiple (multi-lateral) subcaches. The data reference stream of a running program is subdivided into two classes, and each class is mapped to a specific subcache whose management policy is more suitable for the access pattern of its class. This sort of selective organization and caching retains more useful data in the L1 Cache, which translates to more cache hits, less cache-memory bus contention and overall improvement in execution time. Our simulations show that a multi-lateral L1 cache of (8+1)KB total size generally performs as well as, and in some cases better than, an ideal multiported 16 KB cache structure in supplying data.

关键词： Microprocessors Clocks Parallel processing Rivers computer architecture Laboratories Spine Resource management Delay Microarchitecture

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On high-bandwidth data cache design for multi-issue processors 30

On high-bandwidth data cache design for multi-issue processo...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： J.A. Rivers G.S. Tyson E.S. Davidson T.M. Austin Advanced Computer Architecture Laboratory University of Michigan USA Microcomputer Research Laboratories Intel Corporation USA

ISBN: (纸本)9780818679773

Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The number of instructions that must be processed (including correctly predicted ones) will approach 16 or more per cycle. Since memory operations account for about a third of all instructions executed these systems will have to support multiple data references per cycle. We explore reference stream characteristics to determine how best to meet the need for ever increasing access rates. We identify limitations of existing multi-ported cache designs and propose a new structure, the locality-based interleaved cache (LBIC), to exploit the characteristics of the data reference stream while approaching the economy of traditional multi-bank cache design. Experimental results show that the LBIC structure is capable of outperforming current multi-ported approaches.

关键词： Process design Clocks Bandwidth Microprocessors Time division multiplexing Costs Rivers computer architecture Laboratories Microcomputers

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CLIP: an optimizing layout generator for two-dimensional CMOS cells 97

CLIP: an optimizing layout generator for two-dimensional CMO...

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Proceedings of the 34th annual Design Automation Conference

作者： Avaneendra Gupta John P. Hayes Advanced Computer Architecture Laboratory Dept. of EECS University of Michigan Ann Arbor MI and Design Technology Intel Corporation 2200 Mission College Blvd. Santa Clara CA Advanced Computer Architecture Laboratory Dept. of EECS University of Michigan Ann Arbor MI

ISBN: (纸本)9780897919203

We present a novel technique CLIP for optimizing both theheight and width of CMOS cell layouts in the two-dimensional (2-D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width W cell . Then, another model generatesa 2-D layout that has width W cell and requires a minimumnumber of routing tracks. Run times are in seconds for circuitswith up to 16 transistors. For larger circuits, we extend CLIP to ahierarchical method HCLIP that places series-connected transistorscontiguously. This reduces run times by up to three orders ofmagnitude, and still yields optimal results in over 80% of cases.

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