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检索条件"机构=Advanced Computer Architecture Laboratory"

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Minimizing branch misprediction penalties for superpipelined processors 27

Minimizing branch misprediction penalties for superpipelined...

引用

27th Annual International Symposium on Microarchitecture, MICRO 1994

作者： Su, Ching-Long Despain, Alvin M. Advanced Computer Architecture Laboratory University of Southern California United States

ISBN: (纸本)0897917073

Branch misprediction penalties depend on branch misprediction rates and branch penalties. Dynamic branch schemes take advantage of hardware to record and predict branch behavior at run-time for reducing branch misprediction rates. Static branch schemes take advantage of scheduling safe instructions into branch delay slots at compile-time for reducing branch penalties. This paper evaluates and compares the performance of various stateof-the-art static and dynamic branch schemes for superpipelined processors. © 1994 ACM.

关键词： Delay Runtime Permission Program processors Pipelines Hardware Processor scheduling Distributed computing Machinery CMOS technology

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A hierarchical approach to modeling and improving the performance of scientific applications on the KSR1

A hierarchical approach to modeling and improving the perfor...

引用

23rd International Conference on Parallel Processing, ICPP 1994

作者： Boyd, E.L. Azeem, W. Lee, Hsien-Hsin Shih, Tien-Pao Hung, Shih-Hao Davidson, E.S. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan United States

We have developed a hierarchical performance bounding methodology that attempts to explain the performance of loop-dominated scientific applications on particular systems. The Kendall Square Research KSR1 is used as a running example. We model the throughput of key hardware units that arc common bottlenecks in concurrent machines. The four units currently used are: memory port, floating-point, instruction issue, and a loop-carried dependence pseudo-unit. We propose a workload characterization, and derive upper bounds on the performance of specific machine-workload pairs. Comparing delivered performance with bounds focuses attention on areas for improvement and indicates how much improvement might be attainable. We delineate a comprehensive approach to modeling and improving application performance on the KSR1. Application of this approach is being automated for the KSR1 with a series of tools including K-MA and K-MACSTAT (which enable the calculation of the MACS hierarchy of performance bounds), K-Trace (which allows parallel code to be instrumented to produce a memory reference trace), and K-Cache (which simulates inter-cache communications based on a memory reference trace). © 1994 IEEE.

关键词： Hierarchical systems

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Branch with masked squashing in superpipelined processors 94

Branch with masked squashing in superpipelined processors

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Proceedings of the 21st annual international symposium on computer architecture

作者： C.-L Su A. M. Despain Advanced Computer Architecture Laboratory University of Southern California

ISBN: (纸本)9780818655104

The performance of a superpipeline processor heavily relies on its branch performance. Traditional branch strategies used in pipelined processors are delayed branches and branch with squashing. Delayed branches use safe instructions to fill delay slots. However, for a deeply pipelined processor, a compiler may not be able to find sufficient safe instructions to fill the branch delay slots. Branch with squashing takes advantage of using instructions in target basic blocks to fill the branch delay slots. However, the penalty of branch misprediction is large in superpipelined *** this paper, we proposed a novel branch scheme, named branch with masked squashing, which takes advantage of both delayed branch and branch with squashing. The basic idea is to fill delay slots with safe instructions which may come from above or after the branch. For the remaining unfilled delay slots, we fill with instructions from the predicted target path. In the case of misprediction, only unsafe instructions are annulled. The safe instructions in branch delay slots are always executed. Simulation results show that this branch strategy performs better than traditional delayed branch and branch with squashing.

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Low power architecture design and compilation techniques for high-performance processors

Low power architecture design and compilation techniques for...

引用

IEEE Compcon

作者： Ching-Long Su Chi-Ying Tsui A.M. Despain Advanced Computer Architecture Laboratory University of Southern California USA

Reducing switching activity would significantly reduce power consumption of a processor chip. The authors present two novel techniques, Gray code addressing and Cold scheduling, for reducing switching activity on high performance processors. They use Gray code which has only one-bit different in consecutive number for addressing. Due to locality of program execution, Gray code addressing can significantly reduce the number of bit switches. Experimental results show that for typical programs running on a RISC microprocessor, using Gray code addressing reduce the switching activity at the address lines by 30/spl sim/50% compared to using normal binary code addressing. Cold scheduling is a software method which schedules instructions in a way that switching activity is minimized. The authors carried out experiments with cold scheduling on the VLSI-BAM. Preliminary results show that switching activity in the control path is reduced by 20-30%.< >

关键词： Energy consumption Reflective binary codes Processor scheduling Biomedical computing Telecommunication computing Circuit synthesis Switching circuits Voltage Logic computer architecture

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Hardware-software co-designing benchmark-driven superpipelined instruction set processors

Hardware-software co-designing benchmark-driven superpipelin...

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IEEE Annual International computer Software and Applications Conference (COMPSAC)

作者： Ching-Long Su A.M. Despain Advanced Computer Architecture Laboratory University of Southern California USA

This paper focuses on the issues of designing an optimal superpipelined ISP (instruction set processor) driven by a set of benchmark programs. Most issues discussed in this paper also apply to VLIW and superscalar pro... 详细信息

关键词： Pipelines Circuits Parallel processing Program processors Throughput Latches Routing Silicon Application software Scheduling

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A study of cache hashing functions for symbolic applications in micro-parallel processors

A study of cache hashing functions for symbolic applications...

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International Conference on Parallel and Distributed Systems (ICPADS)

作者： Ching-Long Su Chen-Chiu Teng A.M. Despain Advanced Computer Architecture Laboratory University of Southern California USA

This paper presents a study of cache hashing functions for micro-parallel processors (e.g., superpipeline and super-scalar processors). Several novel cache hashing functions are experimented. Our simulation results show that an unconventional cache hashing function applied on a direct-mapped cache results in hit rates as good as a two-way set associative cache with traditional mapping, while the cache hit times are as fast as a direct-mapped cache with traditional mapping.

关键词： Application software computer architecture Laboratories Computational modeling VLIW Runtime

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A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1

A Hierarchical Approach to Modeling and Improving the Perfor...

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International Conference on Parallel Processing (ICPP)

作者： E.L. Boyd W. Azeem Hsien-Hsin Lee Hsien-Hsin Lee Tien-Pao Shih Tien-Pao Shih Shih-Hao Hung Shih-Hao Hung E.S. Davidson Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan USA

关键词： Registers Tools Program processors Clocks Mathematical model Schedules Kernel

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DFBT: A Design-for-Testability Method Based on Balance Testing 94

DFBT: A Design-for-Testability Method Based on Balance Testi...

引用

Design Automation Conference

作者： K. Chakrabarty J.P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780897916530

We present design for balance testability (DFBT), a systematic signature-based method for enhancing the testability of logic circuits. DFBT employs balance testing and guarantees 100% coverage of single stuck-line faults, as well as many multiple stuck-line and bridging faults. The logic overhead of DFBT is modest|only one extra I/O pin and a small number of extra gates|and the original circuit need not be altered. We illustrate DFBT by applying it to representative logic circuits.

关键词： Design methodology Circuit testing Circuit faults Logic testing Design for testability Logic circuits System testing Automatic testing Combinational circuits Counting circuits

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Minimum register requirements for a modulo schedule 27

Minimum register requirements for a modulo schedule

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27th Annual International Symposium on Microarchitecture, MICRO 1994

作者： Eichenberger, Alexandre E. Davidson, Edward S. Abraham, Santosh G. Advanced Computer Architecture Laboratory EECS Department University of Michigan Ann ArborMI48109-2122 United States Hewlett Packard Laboratories 1501 Page Mill Road Palo AltoCA94304 United States

ISBN: (纸本)0897917073

Modulo scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a modulo reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive modulo scheduling and is useful in evaluating the performance of lifetime-sensitive modulo scheduling heuristics. © 1994 ACM.

关键词： Heuristic methods

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Minimum register requirements for a module schedule

Minimum register requirements for a module schedule

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： A.E. Eichenberger E.S. Davidson S.G. Abraham EECS Department Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Hewlett Packard Laboratories Palo Alto CA USA

Module scheduling is an efficient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirements. We present a combined approach that schedules the loop operations for minimum register requirements, given a module reservation table. Our method determines optimal register requirements for machines with finite resources and for general dependence graphs. This method demonstrates the potential of lifetime-sensitive module scheduling and is useful in evaluating the performance of lifetime-sensitive module scheduling heuristics.

关键词： Throughput Registers Processor scheduling Laboratories Parallel processing Permission Clocks computer architecture Milling machines Software performance

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