检索结果-内蒙古大学图书馆

National Fiber Optic Engineers Conference, NFOEC 2005

作者： Gumaste, Ashwin Zheng, Si Qing Advanced Computer Network and Architecture Laboratory The University of Texas Dallas TX United States

ISBN: (纸本)1557527849

The growth of RPR in metropolitan optical networks, has been due to the requirement of sub-wavelength granularity and dynamic provisioning between nodes in a 2-ringlet optical network. The solution of creating opto-electro-opto conversion at each node and then processing individually the information being sent on each wavelength leads to expensive equipment cost as well as issues such as strict synchronization and limited bit-rate. Light-trails, on the other hand provides a solution that optically is able to broker the bandwidth between multiple nodes on the same wavelength leading to low cost implementations, while guaranteeing the dynamic bandwidth requirements that are a necessary prelude to provisioning revenue bearing services. A light-trail is a generalization of a lightpath [5], such that multiple nodes on the trail can take part in uni-directional communication within the trail without the need for optical switch reconfiguration. Light-trails can be pragmatically implemented [1] and provide for sub-wavelength optical communication by creating time differentiated flows between individual nodes. In this paper we study the implementation of light-trails to facilitate RPR. Through a simulation study we identify the constraints that affect a light-trail network and how it performs as compared to an RPR network. The intuitive benefit in cost savings using a light-trail network is somewhat offset by the need for aggregation of traffic at the data layer (like RPR) as well as the wastage of bandwidth in the broadcast medium (light-trail). © 2005 OSA.

关键词： Bandwidth

来源：评论

学校读者我要写书评

暂无评论

Sponge: Portable stream programming on graphics engines

Sponge: Portable stream programming on graphics engines

引用

作者： Hormati, Amir Samadi, Mehrzad Woh, Mark Mudge, Trevor Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

Graphics processing units (GPUs) provide a low cost platform for accelerating high performance computations. The introduction of new programming languages, such as CUDA and OpenCL, makes GPU programming attractive to a wide variety of programmers. However, programming GPUs is still a cumbersome task for two primary reasons: tedious performance optimizations and lack of portability. First, optimizing an algorithm for a specific GPU is a time-consuming task that requires a thorough understanding of both the algorithm and the underlying hardware. Unoptimized CUDA programs typically only achieve a small fraction of the peak GPU performance. Second, GPU code lacks efficient portability as code written for one GPU can be inefficient when executed on another. Moving code from one GPU to another while maintaining the desired performance is a non-trivial task often requiring significant modifications to account for the hardware differences. In this work, we propose Sponge, a compilation framework for GPUs using synchronous data flow streaming languages. Sponge is capable of performing a wide variety of optimizations to generate efficient code for graphics engines. Sponge alleviates the problems associated with current GPU programming methods by providing portability across different generations of GPUs and CPUs, and a better abstraction of the hardware details, such as the memory hierarchy and threading model. Using streaming, we provide a writeonce software paradigm and rely on the compiler to automatically create optimized CUDA code for a wide variety of GPU targets. Sponge's compiler optimizations improve the performance of the baseline CUDA implementations by an average of 3.2x. Copyright © 2011 ACM.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Hierarchical coarse-grained stream compilation for software defined radio

Hierarchical coarse-grained stream compilation for software ...

引用

CASES'07: 2007 International Conference on Compilers, architecture, and Synthesis for Embedded Systems

作者： Lin, Yuan Kudlur, Manjunath Mahlke, Scott Mudge, Trevor Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781595938268

Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application specific hardware. The operation throughput requirements of current third-generation (3G) wireless protocols are an order of magnitude higher than the capabilities of modern DSP processors. Due to this steep performance requirement, heterogeneous multiprocessor system-on-chip designs have been proposed to support SDR. Given the difficulty in compiling traditional digital signal processors, these new multiprocessor architectures provide even greater challenges for the programmers and compilers. In this paper, we utilize a hierarchical dataflow programming model, referred to as SPIR, that is designed for modeling SDR applications. We then present a coarse-grained data ow compilation strategy that assigns a SDR protocol's DSP kernels onto multiple processors, allocates memory buffers, and determines an execution schedule that meets a prescribed throughput. Unlike traditional approaches, coarse-grained compilation exploits task-level parallelism by scheduling concurrent DSP kernels instead of instructions. Because of the streaming nature of SDR protocols, we adapted an existing instruction-level software pipelining technique, modulo scheduling, for coarse-grained compilation. Our compilation methodology is able to generate parallel code that achieves near linear speedup on a SDR multiprocessor system. Copyright 2007 ACM.

关键词： Hierarchical systems

来源：评论

学校读者我要写书评

暂无评论

Erasing core boundaries for robust and configurable performance 43

Erasing core boundaries for robust and configurable performa...

引用

Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

作者： Gupta, Shantanu Feng, Shuguang Ansari, Amin Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9780769542997

Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address these issues, a more fundamental change to the fabric of multicore systems is necessary to seamlessly combat these challenges. Towards this end, this paper proposes CoreGenesis, a dynamically adaptive multiprocessor fabric that blurs out individual core boundaries, and encourages resource sharing across cores for performance, fault tolerance and customized processing. Further, as a manifestation of this vision, the paper provides details of a unified performance-reliability solution that can assemble variable-width processors from a network of (potentially broken) pipeline stage-level resources. This design relies on interconnection flexibility, microarchitectural innovations, and compiler directed instruction steering, to merge pipeline resources for high single-thread performance. The same flexibility enables it to route around broken components, achieving sub-core level defect isolation. Together, the resulting fabric consists of a pool of pipeline stage-level resources that can be fluidly allocated for accelerating single-thread performance, throughput computing, or tolerating failures. © 2010 IEEE.

关键词： Reconfigurable architectures

来源：评论

学校读者我要写书评

暂无评论

Embracing heterogeneity with dynamic core boosting 14

Embracing heterogeneity with dynamic core boosting

引用

11th ACM International Conference on Computing Frontiers, CF 2014

作者： Cho, Hyoun Kyu Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781450328708

Uniformly distributing parallel workloads amongst threads is an effective strategy for programmers to increase application performance. However, in any parallel segment, execution time is determined by the longest running thread. Even for embarrassingly parallel programs in the form of SPMD (single program multiple data), the threads are not perfectly balanced due to control flow divergence, non-deterministic memory latencies, and synchronization operations. Such an imbalance can be significantly exacerbated by performance asymmetry among cores, which is likely to exist in future generations of chip multiprocessors (CMPs) either for energy efficiency or due to process variation. We propose Dynamic Core Boosting (DCB), a software-hardware cooperative system that mitigates the workload imbalance problem in performance asymmetric CMPs. Relying on dynamic voltage and frequency scaling to accelerate individual cores at a fine granularity, DCB attempts to balance the workloads by detecting and boosting critical threads. DCB coordinates its compiler and runtime to enable asymmetric CMPs to achieve near-optimal utilization of core boosting. The compiler instruments the program with instructions to give progress hints and the runtime monitors their execution, enabling DCB to intelligently accelerate selected threads within a total core boosting budget for better performance. On a simulated eight core system of varying frequency, our experiments using PARSEC benchmarks show that DCB improves the overall performance by an average of 33%, outperforming a reactive boosting scheme by an average of 10%. © is held by the owner/authors.

关键词： Energy efficiency

来源：评论

学校读者我要写书评

暂无评论

Cache designs for energy efficiency 28

Cache designs for energy efficiency

引用

28th Annual Hawaii International Conference on System Sciences, HICSS 1995

作者： Su, Ching-Long Despain, A.M. Advanced Computer Architecture Laboratory University of Southern California Los AngelesCA United States

ISBN: (纸本)0818669306

Caches usually consume a significant amount of energy in modern microprocessors (e.g. superpipelined or superscalar processors). In this paper, we examine contemporary cache design techniques and provide an analytical model for estimating cache energy consumption. We also present several novel techniques for designing energy-efficient caches, which include block buffering, cache sub-banking, and Gray code addressing. Experimental results suggest that both the block buffering and Gray code addressing techniques are ideal for instruction cache designs which tend to be accessed in a consecutive sequence. Cache sub-banking is ideal for both instruction and data caches. Overall, these techniques can achieve an order of magnitude energy reduction on caches. © 1995 IEEE.

关键词： Energy utilization

来源：评论

学校读者我要写书评

暂无评论

CGRA express: Accelerating execution using dynamic operation fusion

CGRA express: Accelerating execution using dynamic operation...

引用

Embedded Systems Week 2009, ESWEEK 2009 - 2009 International Conference on Compilers, architecture, and Synthesis for Embedded Systems, CASES'09

作者： Park, Yongjun Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9781605586267

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalability, low cost, and energy efficiency. CGRAs have been effectively used for innermost loops that contain an abundant of instruction-level parallelism. Conversely, non-loop and outer-loop code are latency constrained and do not offer significant amounts of instruction-level parallelism. In these situations, CGRAs are ineffective as the majority of the resources remain idle. In this paper, dynamic operation fusion is introduced to enable CGRAs to effectively accelerate latency-constrained code regions. Dynamic operation fusion is enabled through the combination of a small bypass network added between function units in a conventional CGRA and a sub-cycle modulo scheduler to automatically identify opportunities for fusion. Results show that dynamic operation fusion reduced total application run-time by up to 17% on a 4x4 CGRA. Copyright 2009 ACM.

关键词： Memory architecture

来源：评论

学校读者我要写书评

暂无评论

Self-calibrating online wearout detection

Self-calibrating online wearout detection

引用

40th IEEE/ACM International Symposium on Microarchitecture, MICRO 2007

作者： Blome, Jason Feng, Shuguang Gupta, Shantanu Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)0769530478

Technology scaling, characterized by decreasing feature size, thinning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology generations. Physical analysis of device failure mechanisms has shown that most wearout mechanisms projected to plague future technology generations are progressive, meaning that the circuit-level effects of wearout develop and intensify with age over the lifetime of the chip. This work leverages the progression of wearout over time in order to present a low-cost hardware structure that identifies increasing propagation delay, which is symptomatic of many forms of wearout, to accurately forecast the failure of microarchitectural structures. To motivate the use of this predictive technique, an HSPICE analysis of the effects of one particular failure mechanism, gate oxide breakdown, on gates from a standard cell library characterized for a 90 nm process is presented. This gate-level analysis is then used to demonstrate the aggregate change in output delay of high-level structures within a synthesized Verilog model of an embedded microprocessor core. Leveraging this analysis, a self-calibrating hardware structure for conducting statistical analysis of output delay is presented and its efficacy in predicting the failure of a variety of structures within the microprocessor core is evaluated. © 2007 IEEE.

关键词： Failure (mechanical)

来源：评论

学校读者我要写书评

暂无评论

StageNetSlice: A reconfigurable microarchitecture building block for resilient CMP systems

StageNetSlice: A reconfigurable microarchitecture building b...

引用

Embedded Systems Week 2008 - 2008 International Conference on Compilers, architecture and Synthesis for Embedded Systems, CASES'08

作者： Gupta, Shantanu Feng, Shuguang Ansari, Amin Blome, Jason Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9781605584690

Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip temperatures. Given that most wearout mechanisms that plague semiconductor devices are highly dependent on these parameters, significantly higher failure rates are projected for future technology generations. Traditional techniques for dealing with device failures have relied on coarse-grained redundancy to maintain service in the face of failed components. In this work, we challenge this practice by identifying its inability to scale to high failure rate scenarios and investigate the advantages of finer-grained configurations. We use this study to motivate the design of StageNet, an embedded CMP architecture designed from its inception with reliability as a first class design constraint. StageNet relies on a reconfigurable network of replicated processor pipeline stages to maximize the useful lifetime of the chip, gracefully degrading performance toward end of life. This paper addresses the microarchitecture of the basic building block of StageNet, named StageNetSIice, which is a processor core comprised of networked pipeline stages. A naive slice design results in approximately 4X slowdown verses a traditional processor due to longer communication delays in the pipeline. However, several small design changes that eliminate inter-stage communication paths and minimize communication bandwidth reduce this overhead to 11% on average while providing high levels of fine-grain adaptability. Copyright 2008 ACM.

关键词： Integrated circuit design

来源：评论

学校读者我要写书评

暂无评论

Event propagation conditions in circuit delay computation

引用

ACM Transactions on Design Automation of Electronic Systems 1997年第3期2卷 249-280页

作者： Yalcin, Hakan Hayes, John P. Advanced Computer Architecture Laboratory Department Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109-2122 United States

Accurate and efficient computation of delays is a central problem in computer-aided design of complex VLSI circuits. Delays are determined by events (signal transitions) propagated from the inputs of a circuit to its outputs, so precise characterization of event propagation is required for accurate delay computation. Although many different propagation conditions (PCs) have been proposed for delay computation, their properties and relationships have been far from clear. We present a systematic analysis of delay computation based on a series of waveform models that capture signal behavior rigorously at different levels of detail. The most general model, called the exact or W0 model, specifies each event occurring in a circuit signal. A novel method is presented that generates approximate waveforms by progressively eliminating signal values from the exact model. For each waveform model, we derive the PCs that correctly capture the requirements under which an event propagates along a path. The waveform models and their PCs are shown to form a well-defined hierarchy, which provides a means to trade accuracy for computational effort. The relationships among the derived PCs and existing ones are analyzed in depth. It is proven that though many PCs, such as the popular floating mode condition, produce a correct upper bound on the circuit delay, they can fail to recognize event propagation in some instances. This analysis further enables us to derive new and useful PCs. We describe such a PC, called safe static. Experimental results demonstrate that safe static provides an excellent accuracy/efficiency tradeoff. © 1997 ACM.

关键词： Delay computation Event propagation False path Path sensitization Performance Propagation condition Theory Timing analysis Verification Waveform modeling

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：