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Balance testing of logic circuits

Balance testing of logic circuits

引用

International Symposium on Fault-Tolerant Computing (FTCS)

作者： K. Chakrabarty J.P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors propose a new method for testing logic circuits, termed balance testing, which requires no explicit signatures and is particularly attractive for built-in self-testing. It exploits the balance property possessed by many useful Boolean functions: f(X) is balanced if f(X) = 1 for half its input combinations. The authors analyze balance testing by deriving necessary and sufficient conditions for the detectability of single stuck-line, multiple stuck-line, and bridging faults. These conditions help the designer identify individual faults that remain undetected by balance testing. The analysis also obviates the need for error models that are often difficult to validate. Some feasible design techniques to make logic circuits balance testable are demonstrated.

关键词： Circuit testing Logic testing Logic circuits Automatic testing Circuit faults Built-in self-test Boolean functions Sufficient conditions Electrical fault detection Fault detection

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A separation between reconfigurable mesh models

A separation between reconfigurable mesh models

引用

International Symposium on Parallel Processing

作者： P.D. MacKenzie Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The author proves separations between two models of the reconfigurable mesh (rmesh), the cross-over model and the non-cross-over model. Specifically he shows that in the non-cross-over model, a k*n rmesh requires Omega ((log n)/k) time to compute the parity of n bits stored one per column, and a square root n* square root n rmesh requires Omega (log*n) time to compute the parity of n bits stored one per processor. In the cross-over model, in either case, the parity can be computed in constant time. The lower bounds given in this paper are the first separations demonstrated between the cross-over and non-cross-over model. These lower bounds do not rely on the bandwidth constraints of the mesh and do not restrict the instruction sets of the processors. Moreover, they are the first lower bounds for the rmesh which require only binary inputs.< >

关键词： Bandwidth Integrated circuit modeling Concurrent computing Phase change random access memory computer architecture Laboratories Instruction sets Joining processes Partitioning algorithms Computational modeling

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A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus 26

A microarchitectural performance evaluation of a 3.2 Gbyte/s...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Tim Stanley Michael Upton Patrick Sherhart Trevor Mudge Richard Brown Advanced Computer Architecture Laboratory Department of Electrical Engineering-Systems University of Southern California USA Department of Electrical Computer Engineering Drexel University Philadelphia PA USA Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor Michigan

ISBN: (纸本)9780818652806

The conventional classification of inter-instruction dependencies (data, anti and output dependencies) provides a basic scheme for the analysis of pipeline hazards in pipelined instruction set processors. However, it does not consider the relative spatial positions of micro-operations in the pipeline, thus providing limited hints to hardware designers and compiler writers about the hazard resolution in generalized pipeline structures. The authors propose an extension to the conventional classification of dependencies, which is capable of encapsulating the spatial/temporal relationship and providing precise hardware/software resolution strategies. With the extended classification and its associated hardware/software resolution strategies, they are able to systematically analyze the potential register-related pipeline hazards for a given pipeline structure, determine appropriate resolution strategies, and explore the tradeoff between hardware and software complexities. The methodology enables the systematic synthesis of high performance pipelined micro-architectures, and is useful to derive the back-end of the supporting compilers.< >

关键词： Hazards Pipeline processing Hardware Application software computer architecture Laboratories High level synthesis Design automation Throughput System performance

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Parallelization of a finite element code for 3D scattering

Parallelization of a finite element code for 3D scattering

引用

Antennas and Propagation Society International Symposium

作者： A. Chatterjee J.L. Volakis D. Windheiser E. Hao Radiation Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors present the implementation details of a FE-ABC (finite-element absorbing boundary condition) code and describe the numerical considerations involved in optimizing this code. The linear equation solver and the sparse matrix generation were parallelized on the KSR1 (Kendall Square Research) shared-address space distributed-cache architecture with substantial speedup. Benchmarking was also done on the CM-5 (Connection Machine) with encouraging results. The parallel version of the FE-ABC code was run for a 1.5/spl lambda/ /spl times/ 1/spl lambda/ /spl times/ 1/spl lambda/ pec inlet and the monostatic radar cross section compared with measured data for HH-polarization.< >

关键词： Finite element methods Vectors Electromagnetic scattering Sparse matrices Equations Laboratories computer architecture Linear systems Electromagnetic radiation Electromagnetic fields

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An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors 26

An extended classification of inter-instruction dependency a...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Ing-Jer Huang Alvin M. Despain Department of Materiels Science and Mineral Engineering and Materials snd Molecular Research Division Lewrence Berkeley Leboretory University of California Berkeley CA USA Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780818652806

Several architectural innovations intended to reduce access latency and improve overall throughput increase system bandwidth requirements. Bandwidth scales with clock speed, and can be regarded as an architectural resource to be applied to latency reduction. A properly designed bus provides low arbitration latency and delivers high sustained bandwidth. The paper evaluates the performance of 3.2 Gbyte/s peak bandwidth, low-latency arbitration bus connecting a GaAs superscalar CPU to a GaAs memory management unit. A microarchitectural performance model was written in the Verilog hardware description language. Bus transactions characteristic of the SPECint92 benchmarks and other workloads were generated as input. Sustained bandwidths of 1.68 Gbytes/s were achieved with arbitration costs of less than 0.5 cycles per data transfer.< >

关键词： Microarchitecture Bandwidth Delay Gallium arsenide Hardware design languages Technological innovation Throughput Clocks Joining processes Memory management

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Load balancing requires ω(logß n) expected time 3

Load balancing requires ω(logß n) expected time

引用

3rd Annual ACM-SIAM Symposium on Discrete Algorithms. SODA 1992

作者： MacKenzie, Philip D. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)089791466X

In order to obtain very fast parallel algorithms, it is almost always necessary to have some sort of load balancing procedure, so that processors which have finished their required tasks can help processors which have not. If the overloaded processors are not helped, then the expected time of the entire algorithm suffers. In general, we would like to distribute the remaining work as evenly as possible among the processors, or more formally, given at most n independent tasks distributed in an arbitrary way among n processors, we would like to redistribute the tasks so that each processor contains O(1) tasks. We show here that even on the strongest randomized CRCW PRAM model, for a simple random distribution of tasks load balancing requires ω(logß n) expected time. Gil, Matias, and VishHn [9] give an 0(logß n) expected time randomized algorithm which solves the load balancing problem in the worst case, so the lower bound is tight. By reduction we show that both Padded Sort [12], and Linear Approximate Compaction [13] require Œ(logß w) expected time. We note that our basic technique is one of the few parallel lower bound techniques known which only require 0/1 inputs. We also note that the bounds given in this paper do not place any restriction on the instruction set of the machine, the amount of information which can be stored in a memory cell, or on the number of memory cells.

关键词： Memory architecture

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GaAs RISC processors 14

GaAs RISC processors

引用

14th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, GaAs IC 1992

作者： Brown, R.B. Barker, P. Chandna, A. Huff, T.R. Kayssi, A.I. Lomax, R.J. Mudge, T.N. Nagle, D. Sakallah, K.A. Sherhart, P.J. Uhlig, R. Upton, M. Solid State Electronics Laboratory Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109-2122 United States

ISBN: (纸本)0780307739

A simplified version of a RISC microprocessor has been implemented with E/D MESFET DCFL in the Vitesse HGaAs II process. This chip was designed to drive the development of digital GaAs design automation tools. The processor architecture was modified to fit DCFL technology. The 60, 500-transistor circuit executes a set of 29 basic instructions. It dissipates 11 W and operates at over 100 MHz. The RISC processor chip set being developed in this project is helping to identify the challenges and opportunities of VLSI GaAs. © 1992 IEEE.

关键词： Gallium arsenide

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Delay macromodels for point-to-point MCM interconnections

Delay macromodels for point-to-point MCM interconnections

引用

IEEE Conference on Multi-Chip Module

作者： A.I. Kayssi K.A. Sakallah Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Dimensional analysis is used to develop a macromodel for point-to-point multichip module (MCM) interconnect delay, which applies to lossless and lossy lines. The equation for lossless lines is linear and very simple; the equation for lossy lines is quadratic. In terms of computational costs, the evaluation of delay involves 24 multiplications, and is several orders of magnitude faster than using circuit simulation or transmission line analysis programs to calculate delays. Using the macromodel, the authors derived the dependence of delay on several technology parameters, and calculated the sensitivity of delay to the circuit parameters.< >

关键词： Capacitance Delay effects Driver circuits Distributed parameter circuits Integrated circuit interconnections Semiconductor device modeling Capacitors Equations Inductance Impedance

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Test-set preserving logic transformations

Test-set preserving logic transformations

引用

Design Automation Conference

作者： M.J. Batek J.P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Logic transformations that preserve minimal or complete test sets of a combinational circuit are examined. Some basic transformation types are rigorously defined and characterized with respect to test-set preservation. The authors apply the transformations to adder design and show that any complete test set for a two-level adder is preserved on transformation to ripple-carry and carry-lookahead designs, thus verifying some recent simulation results.< >

关键词： Logic testing Circuit testing Circuit faults Fault detection Adders Circuit synthesis Electrical fault detection Circuit simulation Logic circuits Delay estimation

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GaAs RISC processors

GaAs RISC processors

引用

Annual IEEE Symposium on Gallium Arsenide Integrated Circuit (GaAs IC)

作者： R.B. Brown P. Barker A. Chandna T.R. Huff A.I. Kayssi R.J. Lomax T.N. Mudge D. Nagle K.A. Sakallah P.J. Sherhart R. Uhlig M. Upton Solid State Electronics Laboratory and Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A simplified version of a RISC (reduced instruction set computer) microprocessor has been implemented with E/D MESFET DCFL (direct coupled FET logic) in the Vitesse HGaAs II process. This chip was designed to drive the development of digital GaAs design automation tools. The processor architecture was modified to fit DCFL technology. The 60,500-transistor circuit executes a set of 29 basic instructions. It dissipates 11 W and operates at over 100 MHz.< >

关键词： Gallium arsenide Reduced instruction set computing computer aided instruction Microprocessors MESFETs Coupling circuits FETs Logic Design automation computer architecture

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