Proposes some basic language extensions to incorporate a parallel procedure model into the C programming language. In order to improve on other proposals, the authors set the goals of their design to attain increased ...
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Proposes some basic language extensions to incorporate a parallel procedure model into the C programming language. In order to improve on other proposals, the authors set the goals of their design to attain increased efficiency, flexibility, and expressiveness, and to improve parallel program structure. They begin by discussing the motivation for these goals, and then present an overview of their proposed model for parallel procedures. They then describe the design of the run-time system that supports the parallel procedure model. A novel scheme for nesting parallel procedure contexts in multiple stack frames is included in the run-time system, thus eliminating the need for costly process control blocks. After describing the details of the language and run-time system design, the authors then present detailed performance data for two parallel programs using this system.< >
This paper describes experiences gained during the process of implementing a standard serial bench-mark (SLALOM) on a distributed computing system (Pleiades running ESP). The purpose of the authors experiments has bee...
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This paper describes experiences gained during the process of implementing a standard serial bench-mark (SLALOM) on a distributed computing system (Pleiades running ESP). The purpose of the authors experiments has been to maximize the speedup of a distributed implementation of SLALOM when compared to its serial implementation.< >
A formal methodology is presented for the layout of a single CMOS functional cell and an array of such cells, which addresses height minimization as well as the usual width minimization. Exact layout algorithms are pr...
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ISBN:
(纸本)0818691492
A formal methodology is presented for the layout of a single CMOS functional cell and an array of such cells, which addresses height minimization as well as the usual width minimization. Exact layout algorithms are presented, which are the first to minimize width and height for all cells of practical size, and are computationally feasible for these circuits. The results of a comprehensive set of experiments in which the authors generated layouts for all practical-sized circuits are presented. The optimal layouts are compared to published designs, most of which are based on nonoptimal heuristics. It is shown that not only do these optimal algorithms yield significant area savings, but they also incur little penalty in computation time.
It has been shown previously that given n items and a polynomial number of processors, sorting these items into n locations requires Ω(log n/log log n) time. We sidestep this lower bound with a new technique called P...
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A general theory for designing minimum-area layouts of static series-parallel CMOS functional cells (also called complex gates) in a standard cell layout style is presented. T. Uehara and W.M. vanCleemput. (1981) orig...
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A general theory for designing minimum-area layouts of static series-parallel CMOS functional cells (also called complex gates) in a standard cell layout style is presented. T. Uehara and W.M. vanCleemput. (1981) originally formulated this as the graph optimization problem of finding the minimum number of dual trails that cover a multigraph model of M of a cell. The present theory provides a formalism for the analysis of series-parallel graphs and identifies the mathematical structures that underlie the layout problem. It also leads to two efficient algorithms for designing minimum area functional cell layouts. The first algorithm, TrailTrace, accepts an ordering of M that is fixed, typically for performance reasons, and produces the minimum area layout for that ordering. Its time complexity is linear in the number of transistors in the cell. The second algorithm, R-TrailTrace, reorders M and produces the best layout area that can be achieved for any reordering that preserves the cell's functionality.< >
We have been investigating an approach to parallel database processing based on treating Entity-Relationship (E-R) schema graphs as dataflow graphs. A prerequisite is to find appropriate embeddings of the schema graph...
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We have been investigating an approach to parallel database processing based on treating Entity-Relationship (E-R) schema graphs as dataflow graphs. A prerequisite is to find appropriate embeddings of the schema graphs into a processor graph, in this case a hypercube. This paper studies a class of adjacency preserving embeddings that map a node in the schema graph into a subcube ( relaxed squashed or RS embeddings) or into adjacent subcubes (relaxed extended squashed or RES embeddings) of a hypercube. The mapping algorithm is motivated by the technique used for state assignment in asynchronous sequential machines. In general, the dimension of the cube required for squashed embedding of a graph is called the weak cubical dimension or WCD of the graph. The RES embedding provides an RES-WCD of O (⌈log 2 n ⌉) for a completely connected graph, K n , and RS embedding provides an RS-WCD of O (⌈log 2 n ⌉ + ⌈log 2 m ⌉) for a completely connected bigraph, K m , n . Typical E-R graphs are incompletely connected bigraphs. An algorithm for embedding incomplete bigraphs is presented.
We investigate the design of fault-tolerant (FT) embedding functions of application graphs into hypercubes with the aim of minimizing the recovery cost and performance degradation due to faults. The recovery cost is m...
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