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Proceedings of the 1990 ACM/IEEE conference on Supercomputing

作者： Ram Raghavan John P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor Michigan

ISBN: (纸本)9780897914123

Memory address interleaving, where an address k generated by a processor is mapped into the memory bank k (mod m), is a basic technique for increasing memory bandwidth. However, the access conflicts that can occur in interleaved memories sometimes reduce the bandwidth gain significantly, especially in vector processors. Recently, a few random interleaving schemes have been proposed to reduce memory contention. We define a class of such methods, called LINEAR, that uses linear transformations of addresses for randomization and includes those used in the RP3 and Cydra 5 computers. After identifying a basic deficiency of LINEAR, we define a new class of random interleaving methods called RANDOM-H and, through comparative analysis, show that RANDOM-H performs better than LINEAR. To illustrate RANDOM-H, we describe MASH, which is a random interleaving technique based on multiplicative hashing. Our simulation results indicate that MASH generally performs better than typical linear methods.

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On randomly interleaved memories

On randomly interleaved memories

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Supercomputing Conference

作者： R. Raghavan J.P. Hayes Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The authors analyze and identify a basic deficiency of a class of random interleaving schemes (LINEAR), which use linear transformation techniques to achieve randomization. Since all bank addresses generated by these methods are random, constrained only by the bijective property, more conflicts tend to occur than in the more common MODULO method. Also LINEAR lacks the capability of MODULO to move several conflicting vector streams to a conflict-free steady state. To correct these deficiencies, a new class of random interleaving schemes called RANDOM-H that hash only the higher-order address bits is proposed. Unlike LINEAR, the RANDOM-H schemes randomize selectively, while retaining some of the advantages of MODULO. It is shown that RANDOM-H has a higher probability of accessing a vector without conflict than LINEAR. An an example of RANDOM-H, a method called MASH is presented that combines module interleaving with a multiplicative hashing function for randomization.< >

关键词： Interleaved codes Random access memory Bandwidth Hardware Delay computer architecture Laboratories Vector processors Performance analysis Multi-stage noise shaping

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Practical hypercube algorithms for computational geometry

Practical hypercube algorithms for computational geometry

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Frontiers of Massively Parallel Computation

作者： P.D. MacKenzie Q.F. Stout Advanced Computer Architecture Laboratory Depanment of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The use of the cross-stitching technique to solve problems in computational geometry on the hypercube is discussed. Given n inputs distributed one per processor on a hypercube with n processors. The cross-stitching paradigm runs in Theta (log/sup 2/n) time with very low constants. This form of 2-D divide-and-conquer is illustrated, some of its applications are considered, and its practicality is shown by the computation of exact communication constants for the authors' algorithms.< >

关键词： Hypercubes Computational geometry computer architecture Concurrent computing Euclidean distance Laboratories Phase change random access memory Parallel machines Nearest neighbor searches

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Quick Recovery of Embedded Structures in Hypercube computers

Quick Recovery of Embedded Structures in Hypercube Computers

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Distributed Memory Computing Conference

作者： Tze Chiang Lee Advanced Computer Architecture Laboratory Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA

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computer-SYSTEM architecture CONCEPTS FOR FUTURE COMBAT SYSTEMS

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 43-62页

作者： ZITZMAN, LH FALATKO, SM PAPACH, JL Dr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin

This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computer architecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computer architecture to a general architecture for the future. The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st

关键词： computer architecture

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Parallel branch and bound algorithms on hypercube multiprocessors 3

Parallel branch and bound algorithms on hypercube multiproce...

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3rd Conference on Hypercube Concurrent computers and Applications, C3P 1988

作者： Abdelrahman, Tarek S. Mudge, Trevor N. Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann ArborMI48109 United States

ISBN: (纸本)0897912780

Branch and Bound (BB) algorithms are a generalization of many search algorithms used in Artificial Intelligence and Operations Research. This paper presents our work on implementing BB algorithms on hypercube multiprocessors. The O-l integer linear programming (ILP) problem is taken as an example because it can be implemented to capture the essence of BB search algorithms without too many distracting problem specific details. A BB algorithm for the & ILP problem is discussed. Two parallel implementations of the algorithm on hypercube multiprocessors are presented. The two implementations demonstrate some of the tradeoffs involved in implementing these algorithms on multiprocessors with no shared memory, *** as hypercubes. Experimental results from the NCUBE/six show the performance of the two implementations of the algorithm. Future research work is discussed. © ACM 1988 0-89791-278-0/88/0007/1592.

关键词： Operations research

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Capturing Designer Expertise The CGEN System

Capturing Designer Expertise The CGEN System

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Design Automation Conference

作者： W.P. Birmingham D.P. Siewiorek Advanced Computer Architecture Laboratory Electrical Engineering and Computer Science Department University of Michigan Ann Arbor MI USA Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Knowledge-based systems are becoming pervasive in the computer-aided design area. For these systems to achieve satisfactory levels of performance large amounts of knowledge are necessary; however, the acquisition of knowledge is a difficult task. Automated knowledge-acquisition tools (AKAT) provide capabilities for quickly building and maintaining knowledge-bases. This paper describes CGEN, a tool which allows hardware designers, unfamiliar with artificial intelligence, to deposit their expertise into a knowledge-base. A set of experiments which tested CGEN's capabilities are presented. The experiments demonstrate hardware designers can produce high quality knowledge-bases using CGEN.

关键词： Knowledge based systems Hardware Problem-solving Design automation Knowledge engineering Permission computer architecture Laboratories Buildings Artificial intelligence

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An automorphic approach to the design of fault-tolerant multiprocessors

An automorphic approach to the design of fault-tolerant mult...

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International Symposium on Fault-Tolerant Computing (FTCS)

作者： S. Dutt J.P. Hayes Dept. of Electr. Eng. & Comput. Sci. Michigan Univ. Ann Arbor MI USA Advanced Computer Architecture Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A general and systematic approach to the design of fault-tolerant multiprocessors modeled by graphs is developed. The approach is based on graph automorphisms and is applicable to any graph structure and any degree of fault tolerance. In addition, it incorporates other useful design criteria such as incremental design, low redundancy, and efficient reconfigurability. The authors apply their approach directly to a class of regular multiprocessor graphs termed 'circulant'. For noncirculant graphs, they give an algorithm to construct their circulant edge supergraphs efficiently. They show that the automorphic design method is amenable to efficient implementation using switched redundant links. An application of the foregoing theory to the design of a fault-tolerant hypercube multiprocessor is described.< >

关键词： Fault tolerance Fault tolerant systems Design methodology Tree graphs computer architecture Laboratories Design engineering computer science Redundancy Hypercubes

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TECHNOLOGY GAMING

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NAVAL ENGINEERS JOURNAL 1989年第3期101卷 240-250页

作者： PACE, DK MORAN, DD Dale K. Pace Th.D.:is a member of the Principal Professional Staff of The Johns Hopkins University Applied Physics Laboratory (APL). He currently serves as the APL liaison with the Naval War College where as an adjunct professor he conducts a course on technology and naval warfare. He also teaches in the graduate technical management curriculum of the Whiting School of Engineering at The Johns Hopkins University. His professional responsibilities have included various leadership roles in the Military Operations Research Society the Summer Computer Simulation Conference and simulation conferences in Japan and China the American Society of Engineering Management and chairmanship of the ASNE Journal Committee. David D. Moran Ph.D.:is assistant technical director of the David Taylor Research Center. He also holds the position of adjunct full professor at The George Washington University. Dr. Moran is a graduate of MIT and the University of Iowa in the fields of hydrodynamics and naval architecture. His current responsibilities for the David Taylor Research Center involve long range development of advanced technical and management interactions and strategic planning for the future role of the Center in the Navy RDT&E Laboratory system.

Wise investment of Department of Defense research and development (R&D) resources is becoming increasingly important. R&D policymakers and managers use a variety of means to guide their decisions. This paper discusses one of them: technology gaming. Technology gaming is a complement to traditional methods of technology forecasting, with technology gaming providing insights about constraints imposed upon advanced systems and technologies by operational environments and about their interactions with one another. The potential and practice of technology gaming are described, drawing upon experiences acquired from several technology gaming endeavors in 1988, including the Technology Initiatives 88 Game (TIG-88) performed at the Naval War College under the joint-sponsorship of the Office of Research, Development, and Acquisition in OpNav (OP-098) and the Naval War College.

关键词： Technological Forecasting

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Routing and broadcasting in faulty hypercube computers 3

Routing and broadcasting in faulty hypercube computers

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3rd Conference on Hypercube Concurrent computers and Applications, C3P 1988

作者： Lee, Tze Chiang Hayes, John P. Advanced Computer Architecture Laboratory Electrical Engineering and Computer Science Department University of Michigan Ann ArborMI48109 United States

ISBN: (纸本)0897912780

This paper examines routing and broadcasting algorithms for hypercube computers subject to node failures. First some simple message-passing algorithms are described which perform well with certain fault patterns, but poorly with others. The concept of an unsafe node is introduced to identify fault-free nodes that may cause communication difficulties in faulty hypercubes. It is then shown that by only using "feasible" paths that try to avoid unsafe nodes, routing and broadcasting can be substantially simplified. It is assumed that each active node is supplied with the fault status of all neighboring nodes within a specified radius k. A computationally efficient routing algorithm is presented which can route a message via a path of length no greater than p+2, where p is the minimum feasible distance from the source to the destination, provided that not all non-faulty nodes in the hypercube are unsafe, and k = 1. We further show that broadcasting can be achieved under the same fault conditions with only one more time unit than the fault-free case.

关键词： Broadcasting

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