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A Survey on Graph Neural Network Acceleration: A Hardware Perspective

Chinese Journal of Electronics 2024年第3期33卷 601-622页

作者： Shi CHEN Jingyu LIU Li SHEN School of Computer National University of Defense Technology Key Laboratory of Advanced Microprocessor Chips and Systems

Graph neural networks(GNNs) have emerged as powerful approaches to learn knowledge about graphs and *** rapid employment of GNNs poses requirements for processing *** to incompatibility of general platforms,dedicated hardware devices and platforms are developed to efficiently accelerate training and inference of *** conduct a survey on hardware acceleration for *** first include and introduce recent advances of the domain,and then provide a methodology of categorization to classify existing works into three ***,we discuss optimization techniques adopted at different *** finally we propose suggestions on future directions to facilitate further works.

关键词： Graph neural networks Deep learning acceleration Domain-specific architecture Hardware accelerator

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A comprehensive survey on graph neural network accelerators

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Frontiers of computer Science 2025年第2期19卷 11-29页

作者： Jingyu LIU Shi CHEN Li SHEN School of Computer National University of Defense TechnologyChangsha 410073China Key Laboratory of Advanced Microprocessor Chips and Systems Changsha 410073China

Deep learning has gained superior accuracy on Euclidean structure data in neural *** a result,nonEuclidean structure data,such as graph data,has more sophisticated structural information,which can be applied in neural networks as well to address more complex and practical ***,actual graph data obeys a power-law distribution,so the adjacent matrix of a graph is random and *** processing accelerator(GPA)is designed to handle the problems ***,graph computing only processes 1-dimensional *** graph neural networks(GNNs),graph data is ***,GNNs include the execution processes of both traditional graph processing and neural network,which have irregular memory access and regular computation,*** obtain more information in graph data and require better model generalization ability,the layers of GNN are deeper,so the overhead of memory access and computation is *** present,GNN accelerators are designed to deal with this *** this paper,we conduct a systematic survey regarding the design and implementation of GNN ***,we review the challenges faced by GNN accelerators,and existing related works in detail to process ***,we evaluate previous works and propose future directions in this booming field.

关键词： graph neural network accelerators graph convolutional networks design space exploration deep learning domain-specific architecture

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Decomposition-based learning in drone-assisted wireless-powered mobile edge computing networks

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Digital Communications and Networks 2024年第6期10卷 1769-1781页

作者： Xiaoyi Zhou Liang Huang Tong Ye Weiqiang Sun State Key Laboratory of Advanced Optical Communication Systems and Networks Shanghai Jiao Tong UniversityShanghai 200240China College of Computer Science and Technology Zhejiang University of TechnologyHangzhou 310058China

This paper investigates the multi-Unmanned Aerial Vehicle(UAV)-assisted wireless-powered Mobile Edge Computing(MEC)system,where UAVs provide computation and powering services to mobile *** aim to maximize the number of completed computation tasks by jointly optimizing the offloading decisions of all terminals and the trajectory planning of all *** action space of the system is extremely large and grows exponentially with the number of *** this case,single-agent learning will require an overlarge neural network,resulting in insufficient ***,the offloading decisions and trajectory planning are two subproblems performed by different executants,providing an opportunity for *** thus adopt the idea of decomposition and propose a 2-Tiered Multi-agent Soft Actor-Critic(2T-MSAC)algorithm,decomposing a single neural network into multiple small-scale *** the first tier,a single agent is used for offloading decisions,and an online pretrained model based on imitation learning is specially designed to accelerate the training process of this *** the second tier,UAVs utilize multiple agents to plan their *** agent exerts its influence on the parameter update of other agents through actions and rewards,thereby achieving joint *** results demonstrate that the proposed algorithm can be applied to scenarios with various location distributions of terminals,outperforming existing benchmarks that perform well only in specific *** particular,2T-MSAC increases the number of completed tasks by 45.5%in the scenario with uneven terminal ***,the pretrained model based on imitation learning reduces the convergence time of 2T-MSAC by 58.2%.

关键词： Mobile-edge computing Multi-agent reinforcement learning Offloading decision Trajectory planning Unmanned aerial vehicle Wireless power transfer

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Multi-Scale Time Series Segmentation Network Based on Eddy Current Testing for Detecting Surface Metal Defects

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IEEE/CAA Journal of Automatica Sinica 2025年第3期12卷 528-538页

作者： Xiaorui Li Xiaojuan Ban Haoran Qiao Zhaolin Yuan Hong-Ning Dai Chao Yao Yu Guo Mohammad S.Obaidat George Q.Huang the School of Intelligence Science and Technology University of Science and Technology Beijing the Beijing Advanced Innovation Center for Materials Genome Engineering the Key Laboratory of Intelligent Bionic Unmanned Systems and the Institute of Materials Intelligent Technology Liaoning Academy of Materials IEEE the Department of Computer Science Hong Kong Baptist University the School of Computer and Communication Engineering Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education University of Science and Technology Beijing the Beijing Advanced Innovation Center for Materials Genome Engineering University of Science and Technology Beijing the School of Computer and Communication Engineering University of Science and Technology Beijing the King Abdullah Ⅱ School of Information Technology The University of Jordan the Department of Computational Intelligence the School of Computing SRM University the School of Engineering The Amity University The Hong Kong Polytechnic University

In high-risk industrial environments like nuclear power plants, precise defect identification and localization are essential for maintaining production stability and safety. However, the complexity of such a harsh environment leads to significant variations in the shape and size of the defects. To address this challenge, we propose the multivariate time series segmentation network(MSSN), which adopts a multiscale convolutional network with multi-stage and depth-separable convolutions for efficient feature extraction through variable-length templates. To tackle the classification difficulty caused by structural signal variance, MSSN employs logarithmic normalization to adjust instance distributions. Furthermore, it integrates classification with smoothing loss functions to accurately identify defect segments amid similar structural and defect signal subsequences. Our algorithm evaluated on both the Mackey-Glass dataset and industrial dataset achieves over 95% localization and demonstrates the capture capability on the synthetic dataset. In a nuclear plant's heat transfer tube dataset, it captures 90% of defect instances with75% middle localization F1 score.

关键词： Eddy current testing nondestructive testing semantic segmentation time series analysis

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Dalea:A Persistent Multi-Level Extendible Hashing with Improved Tail Performance

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Journal of computer Science & technology 2023年第5期38卷 1051-1073页

作者：熊子威蒋德钧熊劲 Ren Ren Center for Advanced Computer Systems Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 101408China Huawei Technology Co. Ltd.Shanghai 201206China

Persistent memory(PM)promises byte-addressability,large capacity,and *** memory systems,such as key-value stores and in-memory databases,benefit from such features of *** to the great popularity of hash-ing index in main memory systems,a number of research efforts are made to provide high average performance persistent ***,suboptimal tail performance in terms of tail throughput and tail latency is still observed for existing persistent *** this paper,we analyze major sources of suboptimal tail performance from key design issues of persis-tent *** identify the global hash structure and concurrency control as remaining explorable design spaces for im-proving tail *** propose Directory-sharing Multi-level Extendible Hashing(Dalea)for *** designs an-cestor link-based extendible hashing as well as fine-grained transient lock to address the two main sources(rehashing and locking)affecting tail *** evaluation results show that,compared with state-of-the-art persistent hashing Dash,Dalea achieves increased tail throughput by 4.1x and reduced tail latency by ***,in order to provide de-sign guidelines for improving tail performance,we adopt Dalea as a testbed to identify different impacts of four factors on tail performance,including fine-grained rehashing,transient locking,memory pre-allocation,and fingerprinting.

关键词： persistent memory persistent hashing indexing structure

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SSC: An SRAM-Based Silence Computing Design for On-chip Memory 24th

SSC: An SRAM-Based Silence Computing Design for On-chip Mem...

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24th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2024

作者： Chen, Ziming Deng, Quan Hu, Yiyue He, Xiaowei Huang, Libo Wang, Yongwen College of Computer National University of Defense Technology Changsha China Key Laboratory of Advanced Microprocessor Chips and Systems Changsha China

ISBN: (纸本)9789819615445

The rapid development of emerging intelligent applications leads to a surge in computational demands and memory capacity requirements. Compute-in-memory (CIM) is a promising paradigm to alleviate the data movement bottleneck of emerging intelligent applications. SRAM-based CIM technology is employed to enhance the performance of general-purpose processors (e.g., CPU) by reusing on-chip memory (e.g. Cache) for computational tasks. In recent SRAM-based CIM works, peripheral compute circuits, e.g., adder trees, are introduced to improve system performance, as SRAM cells are hard to support arithmetic operations efficiently. However, the excessive peripheral circuit with a large area overhead degrades the memory density, which breaks the balance of computation and memory. To improve the computing capability and memory capability simultaneously of digital-based CIM (DCIM), we propose SSC, an SRAM-based silence computing CIM design, which leverages logic-in-memory operations and peripheral circuits to achieve parallel computing within the SRAM array. We propose 8+T (8T, 9T, and 11T) SRAM bitcells to support majority-of-three (MAJ3), COPY, and NOT logic, which is used to achieve a 3:2 compressor. Furthermore, a silence computing design, facilitated by a local connection between SRAM cells, is proposed to improve system parallelism, which supports parallel logic-in-memory operations and memory access. Our experiment results show that SSC achieves 3.7× memory density improvement compared to prior DCIMs normalized to 12nm. Additionally, the SWaP (TOPS/W×Kb/mm2) figure-of-merit emphasizes the importance of memory density and energy efficiency, showing that this work achieves a higher SWaP of 119.89, which is 1.84× more than prior DCIMs normalized to 12 nm. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： computer circuits

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Critical Path Optimization for Logic Netlists 9

Critical Path Optimization for Logic Netlists

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9th International Conference on Integrated Circuits and Microsystems, ICICM 2024

作者： Yu, Xuewen Huang, Pengcheng Chen, Haiyan Chen, Wei School of Computer National University of Defense Technology Key Laboratory of Advanced Microprocessors Chips and Systems Changsha China School of Computer National University of Defense Technology Department of Computer Science Changsha China

ISBN: (纸本)9798331509453

It is of great concern for high performance microprocessors to optimize logic delay and improve performance in the semi-custom design flow based on commercial standard cell library. To solve this issue, the paper proposes an automated method to optimize the delay of critical path in any block. Firstly, we construct the logic cone for critical paths based on the logic netlist obtained from semi-custom design flow. Secondly, the algorithm conducts large-scale graph partitioning on the logic cone with appropriate constraints. Thirdly, using two-level optimization, we perform logic restructuring on sub graphs resulting from partitioning to get a set of new logic cells. Finally, employing a match algorithm, we pick out high-reusable restructured logic cells for full-custom circuit implementation and replace corresponding circuit structures with them in the logic netlist. The proposed algorithm picks out 5 logic cells for restructuring. Experimental results demonstrate that the approach achieves a reduction in the logic levels and logic delay can be reduced by about 10% after replacing the corresponding structures in the logic netlist. The work effectively reduces critical path delay, which has the potential to enhance the performance of microprocessors. © 2024 IEEE.

关键词： computer circuits

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Hybrid Deadlock Recovery Algorithm for Irregular NoC in Multi-Chiplet systems 22

Hybrid Deadlock Recovery Algorithm for Irregular NoC in Mult...

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22nd IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Chen, Zhiqiang Wang, Yongwen Zhou, Hongwei National University of Defense Technology College of Computer Science and Technology Changsha China Key Laboratory of Advanced Microprocessor Chips and Systems Changsha China

ISBN: (纸本)9798331509712

Dividing a single System-on-Chip (SoC) into multiple chiplets and connecting them using 2.5D packaging technology is becoming a widely adopted approach to enhance chip scale and performance. However, when multiple chiplets are integrated to form a chiplet-based system, the Network-on-Chip (NoC) that interconnects these chiplets can be susceptible to deadlock. Additionally, modularity is a specific concern, as it involves integrating chiplets of different functions, sizes, manufacturing processes, and so on. However, physical layout constraints and potential vertical link failures may result in irregular topologies, which further complicates the design of both fault-tolerant and load-balanced routing algorithms. To tackle these challenges, a Hybrid Deadlock Recovery algorithm for Irregular NoC (HDRI) in multi-chiplet systems is proposed. This algorithm shows adaptability in irregular topologies, additionally exhibiting fault-tolerance capabilities. HDRI features two modes that can dynamically adapt to the network status. Upon detecting a deadlock, it recovers from the deadlock through the coordination of inter-chiplet packets. To be specific, HDRI seeks to break the deadlock by either forwarding or recycling the blocked packets, which respectively correspond to low and high load modes. Experimental results demonstrate that HDRI offers a 7.5% reduction in latency and an area overhead of less than 1.1%. © 2024 IEEE.

关键词： Network-on-chip

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Priority-aware deadlock recovery algorithm for multi-chiplet systems 30

Priority-aware deadlock recovery algorithm for multi-chiplet...

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30th IEEE International Conference on Parallel and Distributed systems, ICPADS 2024

作者： Chen, Zhiqiang Wang, Yongwen Zhou, Hongwei Li, Mengjin National University of Defense Technology College of Computer Science and Technology Changsha China Key Laboratory of Advanced Microprocessor Chips and Systems Changsha China

ISBN: (纸本)9798331515966

In order to tackle complex tasks, multi-chiplet systems integrate various types of chiplets such as CPUs, GPUs, and other accelerators on the active interposer. Interposer Network-on-Chip (NoC) serves as the foundational infrastructure for interconnecting chiplets. The rich and varied traffic characteristics of these chiplets lead to diverse network requirements and pose additional challenges for the design of NoC. Firstly, different chiplets exhibit unique traffic patterns and network requirements. The competition among these different types of chiplets can prevent the system from achieving optimal performance. Secondly, adaptive routing is more adept at managing the dynamic traffic patterns within heterogeneous systems than deterministic routing. However, managing deadlock is critical for network correctness. Prior strategies for deadlock resolution often fail to adequately consider packets of different priorities, potentially hindering overall performance enhancement in multi-chiplet systems. This paper introduces the Priority-Aware Deadlock Recovery Algorithm (PARA) for multi-chiplet systems. By analyzing packet distribution characteristics within a deadlock cycle, it is observed that breaking the deadlock cycle can be accomplished by permitting head-of-line (HoL) blocking packets to depart. Additionally, the Priority-aware FIFO (PFIFO) has been introduced, supporting three modes: normal, priority, and reserve. The proposed PARA achieves a balance between deadlock recovery, HoL blocking alleviation, and priority scheduling. The experimental results indicate that PARA achieves comparable performance with reduced overhead. © 2024 IEEE.

关键词： Network-on-chip

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Nuclei Segmentation in Histopathology Images Using Structure-Preserving Color Normalization Based Ensemble Deep Learning Frameworks

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computers, Materials & Continua 2023年第12期77卷 3077-3094页

作者： Manas Ranjan Prusty Rishi Dinesh Hariket Sukesh Kumar Sheth Alapati Lakshmi Viswanath Sandeep Kumar Satapathy Centre for Cyber-Physical Systems Vellore Institute of TechnologyChennai600127India School of Computer Science and Engineering Vellore Institute of TechnologyChennai600127India Centre for Advanced Data Science Vellore Institute of TechnologyChennai600127India

This paper presents a novel computerized technique for the segmentation of nuclei in hematoxylin and eosin(H&E)stained histopathology *** purpose of this study is to overcome the challenges faced in automated nuclei segmentation due to the diversity of nuclei structures that arise from differences in tissue types and staining protocols,as well as the segmentation of variable-sized and overlapping *** this extent,the approach proposed in this study uses an ensemble of the UNet architecture with various Convolutional Neural Networks(CNN)architectures as encoder backbones,along with stain normalization and test time augmentation,to improve segmentation ***,this paper employs a Structure-Preserving Color Normalization(SPCN)technique as a preprocessing step for stain *** proposed model was trained and tested on both single-organ and multi-organ datasets,yielding an F1 score of 84.11%,mean Intersection over Union(IoU)of 81.67%,dice score of 84.11%,accuracy of 92.58%and precision of 83.78%on the multi-organ dataset,and an F1 score of 87.04%,mean IoU of 86.66%,dice score of 87.04%,accuracy of 96.69%and precision of 87.57%on the single-organ *** findings demonstrate that the proposed model ensemble coupled with the right pre-processing and post-processing techniques enhances nuclei segmentation capabilities.

关键词： Nuclei segmentation image segmentation ensemble U-Net deep learning histopathology image convolutional neural networks

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