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USING VIRTUAL ENVIRONMENTS IN THE DESIGN OF SHIPS

NAVAL ENGINEERS JOURNAL 1994年第3期106卷 91-106页

作者： JONS, OP RYAN, JC JONES, GW Otto P. Jons:received a Diplom Ing. in shipbuilding from the Technical University of Hanover W. Germany and an MS in naval architecture and marine engineering from MIT. He then joined Litton Ship Systems where he was responsible for the preliminary design of the DD-963 hull structure and then for ship system integration as manager LHA ship systems engineering department. From 1972 to 1974 he was the principal research scientist at Hydronautics. In 1974 as technical director he helped establish the Crystal City office of Designers and Planners. Mr. Jons was one of the co-founders of Advanced Marine Enterprises Inc. in 1976 where he serves as corporate vice president engineering. J. Christopher Ryan:earned his bachelors and masters degrees in naval architecture from Webb Institute and MIT respectively. He spent three years at the advanced marine technology division of Litton Industries working on the DD-963 class ship design and related computer aided design projects. He subsequently went to the Navy Department concentrating on early stage design of surface combatants for twelve years including work on the FFG-7 Sea Control Ship CSGN and CVV aircraft carrier projects. He then shifted focus and became the Technical Director for the Computer Supported Design Program in NavSea for five years. Mr. Ryan has served in several supervisory positions within the Ship Design Group in NavSea since that time. He is currently the director of the future ship concepts division. Gary W. Jones:graduated from the University of Tennessee in 1971 with a BS in mechanical engineering and followed up with graduate work at George Washington University and the University of Maryland. Mr. Jones was with the Naval Sea Systems Command from 1971 until 1988 where he was a naval architect in the submarine section of the hull form design division. In 1988 he was detailed to the Defense Advanced Research Projects Agency (DARPA) where he became the program manager for the advanced submarine technology program's hydrodynamic hydroac

A major contributor to the expense and length of time to design, build, and test new systems has been the need to build and test hardware prototypes to determine their effectiveness in meeting operational requirements. Recent and dramatic advances in computer simulation technologies hold forth the promise of revolutionizing design and acquisition strategies by providing the means to validate end users' requirements prior to hardware construction. By designing and operationally testing virtual prototypes in a virtual environment, these technologies will soon offer naval architects the ability to build and launch ships in computer-based cyberspace in lieu of the shipbuilder's ways. The authors of this paper provide the background for these developments, explore the significance and ramifications of these technologies to the current process of ship and system design, outline challenges lying ahead, and present their vision and recommendations for future development.

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Experimental results of two robot arms manipulating large objects

Experimental results of two robot arms manipulating large ob...

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IEEE International Conference on Robotics and Automation (ICRA)

作者： E. Paljug X. Yun Robotic Systems and Advanced Computer Technology Section Jet Propulsion Laboratory Pasadena CA USA General Robotics and Active Sensory Perception (GRASP) Laboratory University of Pennsylvania Philadelphia PA USA

Experimental results for the TRACS testbed, consisting of two PUMA 250 robot arms, are presented. The two arms manipulate a large object by means of an enveloping grasp. A dynamic control algorithm developed for coordinating two robotic arms have been successfully implemented. The results from two experimental tasks in which the two arms move an object while adapting the grasp configuration to the motion trajectory and to an external disturbance force are described in detail.< >

关键词： Manipulators Arm Robot kinematics Force control Laboratories Propulsion Drives System testing Heuristic algorithms Transportation

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Guest Editorial: Focus on Digital Signal Processing Techniques Applied to Space Communications

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European Transactions on Telecommunications 1993年第1期4卷 9-10页

作者： Gaudenzi, Riccardo De Elia, Carlo Harris, Robert A. Rimrdo De Gaudend was born in Rosignano Mmo Italy in 1960. He received the Doctor En- gineer degree (cum Laude) in Electronic Engineering from the University of Pisa. Italy in 1985. From 1986 he was with the European Space Agency (ESA). Stsliow and Communications Engineering Department. Darmrtadt (RFA) where he was involved in satellite telecommunication ground systems design and testing. In particular he followed the development of two new ESA's satellite tracking systems. In 1988 be joined the ESA's Research and Technology Centre (ESTEC). Noordwijk. The Netherlands where is holding a position as releeommunication enginm in the Electrical System Department. He is presently responsible for the definition and development of advanced satellite communication systems. His mull intenst b ddyrducd with effacnt digital modulation and access techniques for fued and mobile wtdlite services synchronization topics and communication systems simulation techniques. Carlo Elia (S'89) was born in Trepuzzi. Italy in 1964. He received the Doctor Engineer degree in Electronic Engineering from Politecnico di Torino. Torino. Italy. in 1989. He his now attending a Doctorate program at PolitanieO di Torino. S i 1990. he has been with the Eurpean Space Agency (ESA) in the Electrical System Department as Tdeeommunications Syrtcm Engineer. His main areas of interest are related to rdvanccd digital modulation and access techniques and channel equalization. R.A. (Bob) Harris (S'69–M'70) received the PhD from the University of Southampton. England in 1971. In 1970 he joined the European Space Agency (then ESRO). based at the European Space Research and Technology Centre (ESTEC) Noordwijk. The Netherlandswas working on telemetry and telecommand systems. Since 1978 he has been Head of the Transmision Techniques Section in the Directorate of Telecom munications. He was involved in the transmission design of the OTS ECS Olympus and European Data Relay systems. He has worked on a wide range of analogue and digital transmission topics wit

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STEREO VISION FOR PLANETARY ROVERS - STOCHASTIC MODELING TO NEAR REAL-TIME IMPLEMENTATION

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INTERNATIONAL JOURNAL OF computer VISION 1992年第1期8卷 71-91页

作者： MATTHIES, L 1. Robotic Systems and Advanced Computer Technology Section Jet Propulsion Laboratory California Institute of Technology 91109 Pasadena CA

NASA scenarios for lunar and planetary missions include robotic vehicles that function in both teleoperated and semi-autonomous modes. Under teleoperation, on-board stereo cameras may provide 3-D scene information to human operators via stereographic displays;likewise, under semi-autonomy, machine stereo vision may provide 3-D information for obstacle avoidance. In the past, the slow speed of machine stereo vision systems has posed a hurdle to the semi-autonomous scenario;however, recent work at JPL and other laboratories has produced stereo systems with high reliability and near real-time performance for low-resolution image pairs. In particular, JPL has taken a significant step by achieving the first autonomous, cross-country robotic traverses (of up to 100 meters) to use stereo vision, with all computing on-board the vehicle. Here, we describe the stereo vision system, including the underlying statistical model and the details of the implementation. The statistical and algorithmic aspects employ random field models of the disparity map, Bayesian formulations of single-scale matching, and area-based image comparisons. The implementation builds bandpass image pyramids and produces disparity maps from the 60 x 64 level of the pyramids at rates of up to two seconds per image pair. All vision processing is done in one 68020 augmented with Datacube image processing boards. We argue that the overall approach provides a unifying paradigm for practical, domain-independent stereo ranging. We close with a discussion of practical and theoretical issues involved in evaluating and extending the performance of the stereo system.

关键词： Obstacle avoidance quasi-realtime language remote operation Low-resolution image Pyramid LUNAR Three Dimensions OUTER PLANETS EXPLORERS Stereoviews Acoustic equipment computer vision Pyramid Stochastic models

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SHIPBOARD DAMAGED STABILITY ASSESSMENT - THE FLOODING CASUALTY CONTROL SOFTWARE

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NAVAL ENGINEERS JOURNAL 1993年第3期105卷 152-166页

作者： ZAHN, PB ROSBOROUGH, J CARLSTROM, R Peter B. Zahn:is a section chief in the Naval Architecture Department at Advanced Marine Enterprises. He is responsible for software development and special trials support. He has led the Flooding Casualty Control Software (FCCS) development effort since joining AME in 1989. He is also responsible for the material handling strikedown and stowage (MHS&S) software development program as well as special trials support for the ACVLAP and T-AGOS 19 programs. Prior to joining AME Mr. Zahn spent nine years with various companies of the ARCTEC Group. His experience includes field trials in venues from the Caribbean to the Bering Sea as well as model tests and engineering design and development efforts. Mr. Zahn received his B.S. in naval architecture and marine engineering from Webb Institute in 1980 and has published various papers on pollution prevention offshore systems and icebreaker design and performance. He is a member of ASNE and SNAME. John Rosborough:has been a naval architect for the Naval Sea Systems Command (NavSea) for the past 15 years. He is currently assigned to the Hydrodynamics Division with responsibility for aircraft carrier stability evaluations and as a task leader for computer-aided ship design development. In the Stability Division he was previously responsible for stability analyses on various amphibious ships SWATHs and foreign ships. He manages the upgrade and augmentation of SHCP at NavSea and is the Navy's technical point of contact for evaluating shipboard stability software and transitioning technology to the fleet. Mr. Rosborough received his B.S. in naval architecture and marine engineering from the University of Michigan in 1977. He is a member of USNI and the Association of Scientists and Engineers at NavSea. Richard Carlstrom:is a naval architect with Advanced Marine Enterprises. He has been responsible for software development in support of a variety of major programs including FCCS and SHCP and is a specialist in stability evaluations for complex ships such as CVs CVNs

The Flooding Casualty Control Software (FCCS) was developed under the auspices of the Naval Sea systems Command (NavSea) and is currently being deployed on a variety of ships in the neets of both the U.S. Navy and the U.S. Coast Guard. The primary objective of FCCS is to enable damage control personnel to identify critical stability conditions, especially when related to the loss of reserve buoyancy due to battle damage and the destabilizing effects of large quantities of firefighting water, in a timely manner. FCCS was initially deploved in 1990. It utilizes the standard algorithms of the Ship Hull Characteristics Program (SHCP). The user interface was designed to allow quick familiarity for shipboard users, primarily the damage control assistant (DCA) and his staff. Intact stability evaluations include the effects of topside icing, high winds, personnel crowding, heavy lifts over the side, high speed turns, and towing. FCCS also supports ballasting analysis for amphibious ships as well as providing bottom reaction and beached stability data for grounding incidents. Bv providing a tool for the ''fuel king'' and DCA to generate the required daily updates on the current ship load and liquids status, FCCS is assured of an accurate baseline in the event of damage. The design allows the evaluation of the ultimate ship stability status for a damage event using simple compartmentation and flooding status inputs. Evaluation of the adequacy of resulting stabilitv, as well as identification of such critical stability parameters as off center loading, margin line immersion, and negative GM, are accomplished by the program. Guidance is provided for the user to initiate appropriate flooding related damage control activities. Initially fitted on USS Oliver Hazard Perry Class frigates, FCCS databases have been for the USCG Hamilton class high endurance cutters, USS Arleigh Burke class Aegis destroyers, and a variety of other U.S. Navy and U.S. Coast Guard ship classes. The progra

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A VLSI neuroprocessor for real-time image flow computing

A VLSI neuroprocessor for real-time image flow computing

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Wai-Chi Fang B.J. Sheu Ji-Chien Lee Advanced Computer Systems and Technology Section California Institute of Technology Pasadena CA USA Department of Electrical Engineering Signal and Image Processing Institute University of Southern California Los Angeles CA USA

A locally connected multi-layer stochastic neural network and its associated VLSI array neuroprocessors have been developed for high-performance image flow computing systems. An extendable VLSI neural chip has been designed with a silicon area of 4.6*6.8 mm/sup 2/ in a MOSIS 2 mu m scalable CMOS process. The mixed analog-digital design techniques are utilized to achieve compact and programmable synapses with gain-adjustable neurons and winner-take-all cells for massively parallel neural computation. Hardware annealing through the control of the neurons' gain helps to efficiently search the optimal solutions. Computing of image flow using one 2 mu m 72-neuron neural chip can be accelerated by a factor of 187 more than a Sun-4/260 workstation. Real-time image flow processing on industrial images is practical using an extended array of VLSI neural chips. Actual examples on moving trucks are presented.< >

关键词： Very large scale integration Neural network hardware Neurons Stochastic systems Neural networks Multi-layer neural network computer networks Silicon CMOS process Analog-digital conversion

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A real-time VLSI neuroprocessor for adaptive image compression based upon frequency-sensitive competitive learning

A real-time VLSI neuroprocessor for adaptive image compressi...

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International Joint Conference on Neural Networks (IJCNN)

作者： W.-C. Fang B.J. Sheu O.T.-C. Chen Jet Propulsion Laboratory Advanced Computer Systems and Technology Section California Institute of Technology Pasadena CA USA Department of Electrical Engineering Signal and Image Processing Institute University of Southern California Los Angeles CA USA

The frequency-sensitive competitive learning (FSCL) algorithm and its associated VLSI neuroprocessor have been developed for adaptive vector quantisation (AVQ). Simulation results show that the FSCL algorithm is capable of producing a good-quality codebook for AVQ at high compression ratios of more than 20 in real time. This VLSI neural-network-based vector quantization design includes a fully parallel vector quantizer and a pipelined codebook generator to provide an effective data compression scheme. It provides a computing capability as high as 3.33 billion connections per second. Its performance can achieve a speedup of 750 compared with SUN-3/60 and a compression ratio of 33 at a signal-to-noise ratio of 23.81 dB.< >

关键词： Very large scale integration Image coding Frequency Neural networks Power capacitors Vector quantization CMOS technology Image reconstruction Speech coding Data compression

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Real-time high-ratio image compression using adaptive VLSI neuroprocessors

Real-time high-ratio image compression using adaptive VLSI n...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： B.J. Sheu W.-C. Fang Department of Electrical Engineering Signal and Image Processing Institute University of Southern California Los Angeles CA USA Jet Propulsion Laboratory Advanced Computer Systems and Technology Section California Institute of Technology Pasadena CA USA

An adaptive VLSI neuroprocessor based on vector quantization algorithm has been developed for real-time high-ratio image compression applications. This VLSI neural-network-based vector quantization (NNVQ) module combines a fully parallel vector quantizer with a pipelined codebook generator for a broad area of data compression applications. The NNVQ module is capable of producing good-quality reconstructed data at high compression ratios more than 20. The vector quantizer chip has been designed, fabricated, and tested. It contains 64 inner-product neural units and a high-speed extendable winner-take-all block. This mixed-signal chip occupies a compact silicon area of 4.6*6.8 mm/sup 2/ in a 2.0- mu m scalable CMOS technology. The throughput rate of the 2- mu m NNVQ module is 2 million vectors per second and its equivalent computation power is 3.33 billion connections per second.< >

关键词： Image coding Very large scale integration Vector quantization Neural networks Data compression High performance computing Clustering algorithms Application software Image reconstruction CMOS technology

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Yield enhancement of wafer scale integrated arrays

Yield enhancement of wafer scale integrated arrays

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International Conference on Wafer Scale Integration

作者： J. Narasimhan K. Nakajima C.S. Rim A.T. Dahbura E.E. Department & Systems Research Center University of Maryland College Park MD USA Design Automation Systems Section Semiconductor Technology Division Electronics and Telecommunications Research Institute Daejeon South Korea E.E. Department Systems Research Center & Institute for Advanced Computer Studies University of Maryland College Park MD USA Computing Systems Research Laboratory AT and T Bell Laboratories Inc. Murray Hill NJ USA

In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defect-free portion of a defective PGA chip with the same architecture. In the present work, the authors consider the problem of yield enhancement along the same lines as above not only for PGAs but also for wafer-scale-integrated arrays. A heuristic algorithm for reconfiguration based on a graph-theoretic formulation of the problem and a polynomial-time exact algorithm for a special case of the problem are presented. The reconfiguration algorithms are evaluated by comparing the routability and wire length of the reconfigured and initial placements of the circuit.< >

关键词： Electronics packaging Integrated circuit yield Design automation Computational modeling Circuit simulation computer simulation Simulated annealing Heuristic algorithms Polynomials

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computer-SYSTEM ARCHITECTURE CONCEPTS FOR FUTURE COMBAT systems

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 43-62页

作者： ZITZMAN, LH FALATKO, SM PAPACH, JL Dr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin

This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computer architecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computer architecture to a general architecture for the future. The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st

关键词： computer Architecture

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