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IEEE India Conference (INDICON)

作者： Anwesh Kabiraj Debojyoti Pal Pushan Bhattacherjee Kingshuk Chatterjee Ritajit Majumdar Debayan Ganguly Information Technology Government college of Engineering and Leather Technology Kolkata India Electrical Engineering Heritage Institute of Technology Kolkata India Computer Science & Engineering Government College of Engineering and Ceramic Technology Kolkata India Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (数字)9781728169163

ISBN: (纸本)9781728169170

Social distancing, leading to lockdown, has been followed as a measure to restrict the spread of COVID-19 infection in almost every country. In this paper, we study the impact of the united States of America's lockdown measures during this pandemic in restricting the spread of infection. We have split the lockdown into two types - hard lockdown and soft lockdown. A hard lockdown is defined as the period when only essential services are provided. On the other hand, in the soft lockdown period, non-essential services are allowed, but with prevailing social distancing measures. Our findings suggest that a properly implemented Hard Lockdown followed by a soft Lockdown is indeed effective in reducing the reproduction number (R 0 ). Although R 0 increases during the soft lockdown, the rate of increase is restricted if the hard lockdown was implemented favorably. As exceptions to this general trend, we have observed that in Washington state Hard Lockdown has failed to reduce R 0 , and Vermont's soft lockdown implementation was successful in controlling the increase in R 0 post-Hard Lockdown.

关键词： COVID-19 Pandemics Conferences Human factors Market research Social factors Testing

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Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test

Fault Coverage of a Test Set on Structure-Preserving Sibling...

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Asian Test Symposium (ATS)

作者： Manobendra Nath Mondal Animesh Basak Chowdhury Manjari Pradhan Susmita Sur-Kolay Bhargab B. Bhattacharya Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India Centre for Cyber-Security New York University USA Dept. of CSE Indian Institute of Technology Kharagpur India

ISBN: (数字)9781728126951

ISBN: (纸本)9781728126968

Most of the Automatic Test Pattern Generation (ATPG) algorithms for digital circuits rely heavily on netlist description that comprises both network interconnect structure among logic gates and the functionality of each gate. The performance of an ATPG tool on a circuit-under-test (CUT) C is determined by the size of the test set T and its fault coverage (FC). Despite extensive research in the field of testing, the following question remains unanswered: Is the structure or the functionality of C dominant in determining FC of a test-set T for C? In this paper, we present empirical evidence in favour of the dominance of structure on FC by randomly selecting a logic gate from a synthesized netlist for C, and replacing it by a different type of gate. Our experiments provide an un-intuitive result that F C of a test-set T for C under the single stuck-at fault model remains nearly the same on other sibling circuits that have identical structure as of C but with different gate functionality, provided these have similar extent of fault redundancy. This observation supports the view that feeding structural information alone may suffice to train machine-learning models that are currently being used to expedite different problems of digital circuit testing and diagnosis.

关键词： Circuit faults Logic gates Redundancy Sociology Statistics Integrated circuit modeling Tools

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Performance-aware test scheduling for diagnosing coexistent channel faults in topology-agnostic networks-on-chip

Performance-aware test scheduling for diagnosing coexistent ...

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作者： Bhowmik, Biswajit Kumar Deka, Jatindra Biswas, Santosh Bhattacharya, Bhargab B. Department of Computer Science and Engineering Indian Institute of Information Technology Kurnool Jagannathagattu Hill Kurnool Andhra Pradesh518007 India Department of Computer Science and Engineering Indian Institute of Technology Guwahati Amingaon Kamrup Guwahati Assam781039 India Department of Electrical Engineering and Computer Science Indian Institute of Technology Bhilai GEC Campus Sejbahar Raipur Chhattisgarh492015 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata 203 B. T. Road Kolkata West Bengal700108 India

High-performance multiprocessor SoCs used in practice require a complex network-on-chip (NoC) as communication architecture, and the channels therein often suffer from various manufacturing defects. Such physical defects cause a multitude of system-level failures and subsequent degradation of reliability, yield, and performance of the computing platform. Most of the existing test approaches consider mesh-based NoC channels only and do not perform well for other regular topologies such as octagons or spidergons, with regard to test time and overhead issues. This article proposes a topology-agnostic test mechanism that is capable of diagnosing on-line, coexistent channel-short, and stuck-at faults in these special NoCs as well as in traditional mesh architectures. We introduce a new test model called Damaru to decompose the network and present an efficient scheduling scheme to reduce test time without compromising resource utilization during testing. Additionally, the proposed scheduling scheme scales well with network size, channel width, and topological diversity. Simulation results show that the method achieves nearly 92% fault coverage and improves area overhead by almost 60% and test time by 98% compared to earlier approaches. As a sequel, packet latency and energy consumption are also improved by 67.05% and 54.69%, respectively, and they are further improved with increasing network size. © 2019 Association for computing Machinery.

关键词： Network-on-chip

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Misinformation Containment in OSNs leveraging Community Structure

Misinformation Containment in OSNs leveraging Community Stru...

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IEEE International Conference on Awareness Science and Technology

作者： Arnab Kumar Ghoshal Nabanita Das Soham Das Department of Computer Science Asutosh College Kolkata India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Microsoft Corporation Redmond U.S.A

With the emergence of Online Social Networks (OSNs) as a major platform of communication, its abuse to spread misinformation has become a major threat to our society. In this paper, we study the misinformation containment problem in OSN. Given a snapshot of the OSN with a set of misinformed nodes, and a budget in terms of maximum number of seed nodes, the problem is to select the seed nodes, referred here as the beacon nodes, to plant the correct information, to minimize and eventually eradicate the misinformation at the earliest. We leverage the community structure of the OSN to select the beacon nodes, prioritizing the Community Boundary Nodes. To the best of our knowledge, this is the first work to exploit the topology of the OSN to combat misinformation spread. A modified form of Independent Cascade Model is followed to study the adversarial propagation of both misinformation and the correct information. Simulation on real data set shows that the proposed algorithm outperforms earlier algorithm significantly in terms of maximum (average) infected time and the point of decline.

关键词： Probabilistic logic Measurement Topology Sociology Statistics Twitter

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Reliability-aware test methodology for detecting short-channel faults in on-chip networks

Reliability-aware test methodology for detecting short-chann...

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作者： Bhowmik, Biswajit Biswas, Santosh Deka, Jatindra Kumar Bhattacharya, Bhargab B. Department of Computer Science and Engineering IIT Guwahati Guwahati781039 India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata Kolkata700108 India

With the advent of rapidly evolving nanoelectronic systems, compact implementation of versatile and dense network-on-chips (NoCs) on a die has emerged as technology-of-choice for multicore computing. However, because of the increased density, NoCs often suffer from various types of manufacturing faults, which degrade the yield and jeopardize the reliability of the overall system. For example, short-channel faults in an NoC often cause system-level failures that may have significant impact on its performance. This paper proposes a cluster-based distributed scheme for online testing of short faults in NoC channels. The proposed algorithm detects both intra and interchannel short faults and identifies the underlying faulty channel-wires connected to a node. The nodes in a cluster-set are appropriately scheduled to reduce test time. The approach scales to larger NoCs irrespective of size of the network and channel width. The proposed scheme also extends its application from regular to irregular NoCs, and to other channel faults like open. Fault simulation shows that the proposed cluster-driven scheme is capable of detecting all modeled short-channel faults. Online evaluation of the scheme also reveals the extent of impact that the short faults impart on various performance metrics for large traffic. Compared to prior work, it reduces hardware area overhead up to 27% and test time by more than 21 × on several test cases. In addition, packet latency and energy consumption are reduced by 19.47%-40.16% and 17.57%-34.20%, respectively. © 1993-2012 IEEE.

关键词： Network-on-chip

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Analyzing the Effect of Soft Handover on Handover Performance Evaluation Metrics under Load Condition

Analyzing the Effect of Soft Handover on Handover Performanc...

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作者： Panigrahy, Nitish K. Ghosh, Sasthi C. College of Information and Computer Sciences University of Massachusetts AmherstMA01003-9264 United States Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata700108 India

With increasing popularity of wireless local area network (WLAN) and emerging real-time applications, seamless mobility has become one of the primary concerns. Hence, the choice of a proper handover algorithm is of utmost importance. Various performance evaluation metrics for handover algorithms have been proposed in this regard. We argue that in a multiple access point (AP) scenario, the load on each of the APs, the requested data rate of the mobile terminal, and the soft handover have significant impact on these metrics. In this paper, we present an analytical framework to measure various handover performance evaluation metrics under both load condition and soft handover for a specific data rate request. Our approach is based on finding the circular region centered around an AP within which the requested data rate can be satisfied. We have considered WLAN usage efficiency, handover failure probability, and unnecessary handover probability as evaluation metrics. We have analyzed the impact of load and soft handover on these metrics. The impact of velocity on these metrics has also been analyzed. We also have derived lower bounds on both handover failure probability and unnecessary handover probability by formulating the problem into three circle intersection problem. The circular coverage assumption used in the framework is also validated through simulation. © 1967-2012 IEEE.

关键词： Efficiency

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Flow-Based Passive Microfluidic Architecture for Homogeneous Mixing

Flow-Based Passive Microfluidic Architecture for Homogeneous...

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International Symposium on Electronic System Design (ISED)

作者： Tapalina Banerjee Sudip Poddar Robert Wille Bhargab B. Bhattacharya Advanced Computing and Microelectronics Unit Indian Statistical Institute University of Calcutta Kolkata India EDA-LAB National Taiwan University of Science and Technology Taiwan Institute for Integrated Circuits Johannes Kepler University Linz Austria Indian Institute of Technology Kharagpur India

ISBN: (数字)9781728141770

ISBN: (纸本)9781728141787

Accurate sample preparation, an essential component in microfluidic design automation, poses a great challenge to lab-on-chip (LoC) designers. Although continuous-flow based microfluidic biochips (CFMBs) offer many advantages, the problem of achieving fast, stable, and controllable sample concentration becomes more pronounced when such chips are used. Most of the flow-based dilutions and/or mixing methods need certain settling time to ensure an output flow with stable concentration profile resulting in initial loss of fluids. Control-valve sequencing along with time management for injecting input fluids further complicates the scenario. In this paper, we address the problem of preparing a homogeneous mixture of several input-fluids with different concentration factors. We present a binary tree-based free-flowing microfluidic architecture, which obviates the need for any control valve. The passive fluidic network supports balanced hydraulic resistance along all input-output fluid paths and ensures low Reynolds number. We show that the homogeneity of mixing can be expedited by properly assigning inlets to fluids with different concentrations based on a graph-matching algorithm. The method reveals how design automation tools can be effectively used for solving a problem of fluid dynamics. Theoretical attributes of the proposed architecture, when compared with COMSOL Multiphysics based simulations, provide excellent agreement with high accuracy.

关键词： Mixers Valves Computer architecture Immune system Computer science

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Dilution with digital microfluidic biochips: How unbalanced splits corrupt target-concentration

arXiv

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arXiv 2019年

作者： Poddar, Sudip Wille, Robert Rahaman, Hafizur Bhattacharya, Bhargab B. Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata700108 India Department of Computer Science & Engineering Indian Institute of Technology Kharagpur721 302 India Indian Statistical Institute Kolkata700108 India School of VLSI Technology Indian Institute of Engineering Science and Technology Shibpur711103 India Institute for Integrated Circuits Johannes Kepler University Linz Austria

Sample preparation is an indispensable component of almost all biochemical protocols, and it involves, among others, making dilutions and mixtures of fluids in certain ratios. Recent microfluidic technologies offer suitable platforms for automating dilutions on-chip, and typically on a digital microfluidic biochip (DMFB), a sequence of (1: 1) mix-split operations is performed on fluid droplets to achieve the target concentration factor (CF) of a sample. An (1: 1) mixing model ideally comprises mixing of two unit-volume droplets followed by a (balanced) splitting into two unit-volume daughter-droplets. However, a major source of error in fluidic operations is due to unbalanced splitting, where two unequal-volume droplets are produced following a split. Such volumetric split-errors occurring in different mix-split steps of the reaction path often cause a significant drift in the target-CF of the sample, the precision of which cannot be compromised in life-critical assays. In order to circumvent this problem, several error-recovery or error-tolerant techniques have been proposed recently for DMFBs. Unfortunately, the impact of such fluidic errors on a target-CF and the dynamics of their behavior have not yet been rigorously analyzed. In this work, we investigate the effect of multiple volumetric split-errors on various target-CFs during sample preparation. We also perform a detailed analysis of the worst-case scenario, i.e., the condition when the error in a target-CF is maximized. This analysis may lead to the development of new techniques for error-tolerant sample preparation with DMFBs without using any sensing operation. Copyright © 2019, The Authors. All rights reserved.

关键词： Digital microfluidics

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Innovative ranking strategy for IPL team formation

arXiv

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arXiv 2019年

作者： Banerjee, Saptarshi Mitra, Arnabi Ganguly, Debayan Majumdar, Ritajit Chatterjee, Kingshuk Department of Computer Science and Engineering Government College of Engineering and Leather Technology Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India Department of Computer Science and Engineering Government College of Engineering and Ceramic Technology

indian Premier League (IPL) is a tournament of twenty over cricket matches. Teams of this tournament are selected via an auction from a pool of players. Each team employs a think-tank to build the best possible team. Few studies have been performed to automate the process of team selection. However, those studies mostly concentrate either on the current form of the players, or their long term performance. In this paper, we have (i) selected traditional features as well as determined some derived features, which are generated from the traditional features, for batsmen and bowlers, (ii) formulated heuristics for clustering batsmen into openers, middle order batsmen and finishers, (iii) formulated heuristics for relative ranking of batsmen and bowlers considering the current performance as well as the experience of each player, and (iv) have proposed two greedy algorithms for team selection where the total credit point of the team and the number of players in each cluster is fixed. Our proposed ranking scheme and algorithm not only determines the best possible team, but can also determine the best alternate player if one of the target players is unavailable. Copyright © 2019, The Authors. All rights reserved.

关键词： Clustering algorithms

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Quantum error-correcting code for ternary logic

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Physical Review A 2018年第5期97卷 052302-052302页

作者： Ritajit Majumdar Saikat Basu Shibashis Ghosh Susmita Sur-Kolay Advanced Computing & Microelectronics Unit Indian Statistical Institute India A.K. Choudhury School of Information Technology University of Calcutta India

Ternary quantum systems are being studied because they provide more computational state space per unit of information, known as qutrit. A qutrit has three basis states, thus a qubit may be considered as a special case of a qutrit where the coefficient of one of the basis states is zero. Hence both (2×2)-dimensional and (3×3)-dimensional Pauli errors can occur on qutrits. In this paper, we (i) explore the possible (2×2)-dimensional as well as (3×3)-dimensional Pauli errors in qutrits and show that any pairwise bit swap error can be expressed as a linear combination of shift errors and phase errors, (ii) propose a special type of error called a quantum superposition error and show its equivalence to arbitrary rotation, (iii) formulate a nine-qutrit code which can correct a single error in a qutrit, and (iv) provide its stabilizer and circuit realization.

关键词： Quantum error correction

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