检索结果-内蒙古大学图书馆

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design

作者： Mitra, Debasis Bhattacharjee, Subhasis Sur-Kolay, Susmita Bhattacharya, Bhargab B. Zachariah, Sujit T. Kundu, Sandip Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India Design/Test Technology India Intel Technology India Pvt. Ltd. Bangalore India Dept of ECE University of Massachusetts Amherst United States

ISBN: (纸本)0769525024

In deep sub-micron VLSI chips, when several tran-sistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow down. Such timing faults are termed as droop faults. Modeling of droop faults and understanding their effects on the functionality and timing behavior of the circuit are yet to be fully understood. In this paper, a new model for droop faults is proposed. A simple ATPG-based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 benchmark circuits reveal that a very high droop fault coverage can be obtained by a short sequence of test vectors. © 2006 IEEE.

关键词： VLSI circuits

来源：评论

学校读者我要写书评

暂无评论

Test pattern generation for power supply droop faults

Test pattern generation for power supply droop faults

引用

International Conference on VLSI Design

作者： D. Mitra S. Bhattacharjee S. Sur-Kolay B.B. Bhattacharya S.T. Zachariah S. Kunduc Advanced Computing & Microelectronics Unit Indian Statistical Institute Kolkata India Design/Test Technology India Intel Technology India Pvt. Ltd. Bangalore India

In deep sub-micron VLSI chips, when several transistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow down. Such timing faults are termed as droop faults. Modeling of droop faults and understanding their effects on the functionality and timing behavior of the circuit are yet to be fully understood. In this paper, a new model for droop faults is proposed. A simple ATPG-based procedure for stuck-at faults has been adapted to test droop faults. For validation of the methodology in combinational circuits, a set of appropriate clusters of gates is selected to cover potential droop-prone regions in a circuit. Experimental results on ISCAS-85 benchmark circuits reveal that a very high droop fault coverage can be obtained by a short sequence of test vectors.

关键词： Test pattern generators Power supplies Circuit faults Circuit testing Switches Timing Very large scale integration Power grids Voltage Combinational circuits

来源：评论

学校读者我要写书评

暂无评论

Self-stabilizing checkpointing algorithm in ring topology 1

引用

7th International Workshop on Distributed computing, IWDC 2005

作者： Mandal, Partha Sarathi Mukhopadhyaya, Krishnendu Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 B T Road Kolkata 700108 India

ISBN: (数字)9783540324287

ISBN: (纸本)3540309594

If the variables used for a checkpointing algorithm have data faults, the algorithm may fail. In this paper, a self-stabilizing checkpointing algorithm is proposed for handling data faults in a ring network. The proposed algorithm can deal with concurrent initiations of checkpointing and at most one data fault per process. However, several processes may be faulty. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Algorithms

来源：评论

学校读者我要写书评

暂无评论

Fast FPGA placement using space-filling curve

Fast FPGA placement using space-filling curve

引用

2005 International Conference on Field Programmable Logic and Applications, FPL

作者： Banerjee, Pritha Bhattacharjee, Subhasis Sur-Kolay, Susmita Das, Sandip Nandy, Subhas C. Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 B. T. Road Kolkata India

ISBN: (纸本)0780393627

In this paper, we propose a placement method for island-style FPGAs, based on recursive bi-partitioning followed by application of space-filling curves. Experimental results of our method show 55% improvement in cost, when compared to random initial placement of the popular tool VPR. The solutions thus obtained require 44.5% fewer moves during final iterative refinement by ultra-low temperature simulated annealing, whereas the quality of solution is on the average 0.1% better. This establishes the utility of the method for fast reconfiguration of FPGA based co-processors. © 2005 IEEE.

关键词： Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

A fast algorithm for point labeling problem 17

A fast algorithm for point labeling problem

引用

17th Canadian Conference on Computational Geometry, CCCG 2005

作者： Roy, Sasanka Bhattacharjee, Subhasis Das, Sandip Nandy, Subhas C. Advanced Computing and Microelectronics Unit Indian Sta-tistical Institute Kolkata700 108 India

In the map labeling problem, we are given a set P = fp1;p2;: : :;png of point sites distributed on a 2D map. The label of a point pi is an axis-parallel rectangle of specified size. The objective is to label maximum number of points on the map so that the placed labels are mutually non-overlapping. Here, we investigate a special class of map labeling problem where (i) the height of the label of each point is the same but its length may be diffierent from the others, (ii) the label of a point pi touches the point at one of its four corners and (iii) it does not obscure any other point in P. We describe an efficient heuristic algorithm for this problem which runs in O(npn) time in the worst case. We run our algorithm as well as the algorithm proposed in [14] on the available benchmarks [13]. The results produced by our algorithm is same as that of [14] in most of the cases, and is one less in few cases. But the time taken by our algorithm is much less than [14]. © 2005 Canadian Conference on Computational Geometry. All rights reserved.

关键词： Heuristic algorithms

来源：评论

学校读者我要写书评

暂无评论

Isothetic polygonal approximations of a 2D object on generalized grid

引用

1st International Conference on Pattern Recognition and Machine Intelligence, PReMI 2005

作者： Bhowmick, Partha Biswas, Arindam Bhattacharya, Bhargab B. Computer Science and Technology Department Bengal Engineering and Science University Shibpur Howrah India Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

ISBN: (纸本)3540305068

Determination of an isothetic polygonal approximation of the outer or inner contour of an object is a challenging problem with numerous applications to pattern recognition and image processing. In this paper, a novel algorithm is presented for constructing the outer (or inner) tight isothetic polygon(s) containing (or filling) an arbitrarily shaped 2D object on a background grid, using a classical labeling technique, The background grid may consist of uniformly or non-uniformly spaced horizontal and vertical lines. Experimental results for both uniform and non-uniform grids of varying sizes have been reported to demonstrate the applicability and efficiency of the proposed algorithm. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Object recognition

来源：评论

学校读者我要写书评

暂无评论

Fast FPGA placement using space-filling curve

Fast FPGA placement using space-filling curve

引用

International Conference on Field Programmable Logic and Applications

作者： P. Banerjee S. Bhattacharjee S. Sur-Kolay S. Das S.C. Nandy Advanced Computing and Microelectronics Unit Indian Statistical Institute Kolkata India

关键词： Field programmable gate arrays Programmable logic arrays Switches Circuits Temperature Simulated annealing Filling Routing Phased arrays Reconfigurable logic

来源：评论

学校读者我要写书评

暂无评论

Mobility tolerant broadcast in mobile ad hoc networks

引用

6th International Workshop on Distributed computing, IWDC 2004

作者： Srimani, Pradip K Sinha, Bhabani P Department of Computer Science Clemson University ClemsonSC29634–0974 United States Advanced Computing and Microelectronics Unit Indian Statistical Institute Calcutta700108 India

ISBN: (纸本)9783540240761

A new deterministic broadcast protocol for an ad hoc network is proposed in this paper which avoids re-computation of the transmission schedule, even when the topology of the network changes due to the mobility of the nodes. The basic idea is to use a successive partitioning scheme by representing the identifier of each node (an integer) in an arbitrarily chosen radix system;the protocol then computes the specific time slots in which a particular node should transmit its message. The proposed protocol is simple, easy to implement and needs lesser broadcast time than that in [BBC99]. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Mobile ad hoc networks

来源：评论

学校读者我要写书评

暂无评论

Efficient Algorithms for Some Common Applications on GHCC

引用

Journal of Interconnection Networks 2005年第4期6卷 417-433页

作者： Srabani Mukhopadhyaya Bhabani P. Sinha Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 B. T. Road Kolkata 700 108 India Advanced Computing and Microelectronics Unit Indian Statistical Institute 203 B. T. Road Kolkaata 700 108 India

Generalized Hypercube-Connected-Cycles (GHCC), is a challenging interconnection network, proposed earlier in the literature. In this paper, we discuss how some important, useful algorithms, like, matrix transpose, matrix multiplication and sorting can efficiently be implemented on GHCC. Matrix transpose and matrix-by-matrix multiplication of matrices of order n × n, , takes O(l) and time, respectively, on GHCC(l,m), with lm l processors. Using the same number of processors, a list of m l numbers can be sorted in O(l 2 log 3 m) time.

关键词： Interconnection networks network topology degree diameter sorting matrix operations

来源：评论

学校读者我要写书评

暂无评论

Collection depots location problem in the plane 17

Collection depots location problem in the plane

引用

17th Canadian Conference on Computational Geometry, CCCG 2005

作者： Benkoczi, Robert Bhattacharya, Binay K. Das, Sandip Sember, Jeff School of Computing Queen's University KingstonONK7L 3N6 Canada School of Computing Science Simon Fraser University Burn-abyBCV5A 1S6 Canada Advanced Computing and Microelectronics Unit Indian Sta- Tistical Institute Calcutta700 035 India

In this paper we consider an extension of the classical facility location problem where besides n customers, a set of p collection depots are also given. In this set- ting the service of a customer consists of the travel of a server to the customer and return back to the center via a collection depot. We have analyzed the problem and showed that the collection depots problem can be trans- formed to O(n2p2) number of different classical facility location problems and this bound is tight. © 2005 Canadian Conference on Computational Geometry. All rights reserved.

关键词： Location

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：